Xilinx Virtex-6 FPGA User Manual page 150

Chapter 3: Transmitter
Figure 3-16
external sequence counter mode, and 64B/67B encoding.
X-Ref Target - Figure 3-16
TXHEADER0
1
TXUSRCLK20
TXSEQUENCE0
37
TXDATA0
10ea 79e6 d48c c995 c9ec 651c 1921 2751 119e 3475 98e9 2043 87c7 a738
The sequence of transmitting 64B/67B data for the external sequence counter mode is:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. On count 65, stop the data pipeline.
11. On count 66, drive data on TXDATA.
The sequence of transmitting 64B/66B data for the external sequence counter mode is:
1.
2.
3.
4.
5.
6.
7.
www.BDTIC.com/XILINX
150
shows how a pause occurs at counter value 44 when using a 2-byte interface,
38 39 40 41 42
Figure 3-16: Pause at Sequence Counter Value 44
Assert TXRESET and wait until the reset cycle is completed.
During reset, drive 7'h00 on TXSEQUENCE, header information on
TXHEADER[2:0], and initial data on TXDATA. This state can be held indefinitely in
readiness for data transmission.
On count 0, drive data to TXDATA and header information to TXHEADER. For a
2-byte interface, drive a second 2 bytes to TXDATA while still on count 0.
The sequence counter increments to 1 while driving data on TXDATA.
After applying 4 bytes of data, the counter increments to 2 and drives data on TXDATA
and header information on TXHEADER[2:0].
On count 21, stop the data pipeline.
On count 22, drive data on TXDATA.
On count 44, stop the data pipeline.
On count 45, drive data on TXDATA.
Assert TXRESET and wait until the reset cycle is completed.
During reset, drive 6'h00 on TXSEQUENCE, header information on
TXHEADER[1:0], and initial data on TXDATA. This state can be held indefinitely in
readiness for data transmission.
On count 0, drive data to TXDATA and header information to TXHEADER[1:0]. For a
2-byte interface, drive a second 2 bytes to TXDATA while still on count 0.
The sequence counter increments to 1 while driving data on TXDATA.
After applying 4 bytes of data, the counter increments to 2 and drives data on TXDATA
and header information on TXHEADER.
On count 31, stop the data pipeline.
On count 32, drive data on TXDATA.
www.xilinx.com
43 44 45 46 47
c5d4 aaeb 2467 0959 aced 0509 0e26 0646 0996 812a e700 b320 6859
Pause for 2 USRCLK2 cycles. Data is ignored.
Virtex-6 FPGA GTX Transceivers User Guide
48 49 50 51
-
UG366_c3_06_051509
UG366 (v2.5) January 17, 2011