Xilinx Virtex-6 FPGA User Manual page 307

Table B-1: Attributes DRP Address Map (Cont'd)
DADDR DRP Bits R/W
15
14:12
11
10
R/W
17h
9:5
4
3
2:0
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Attribute Name
GEN_RXUSRCLK
RX_DATA_WIDTH
CHAN_BOND_SEQ_2_CFG
BIAS_CFG
RX_CLK25_DIVIDER
AC_CAP_DIS
GTX_CFG_PWRUP
OOBDETECT_THRESHOLD
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Attribute Bits Attribute Encoding
FALSE
TRUE
20
8
10
2:0
16
32
40
4 <4:0> 0-31
16
6
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
4:0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
FALSE
TRUE
FALSE
TRUE
2:0 0-7
DRP Binary
Encoding
0
1
011
000
001
010
100
101
(1)
1
00101
00000
00001
00010
00011
00100
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
0
1
0
1
(1)
1
307