Xilinx Virtex-6 FPGA User Manual page 206

Chapter 4: Receiver
Table 4-22: RX CDR Attributes (Cont'd)
Attribute
RX_EYE_SCANMODE
RXPLL_DIVSEL_OUT
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206
Type
2-bit This attribute should be set to 00 for normal operation. Refer to
Binary Analysis, page 210
Integer This divider defines the nominal line rate for the receiver. It can be set to 1,
2, or 4.
RX Line Rate = RX PLL Clock * 2/PLL_RXDIVSEL_OUT
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Description
for detailed information.
Virtex-6 FPGA GTX Transceivers User Guide
RX Margin
UG366 (v2.5) January 17, 2011