Xilinx Virtex-6 FPGA User Manual page 309

Table B-1: Attributes DRP Address Map (Cont'd)
DADDR DRP Bits R/W
15
14:6
R/W
20h
5:1
0
15
21h
14
13:0 R/W
15
22h
14:0
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Attribute Name
TX_OVERSAMPLE_MODE
Reserved
TXPLL_DIVSEL_REF
Reserved
PCI_EXPRESS_MODE
Reserved
TX_DETECT_RX_CFG
PMA_CAS_CLK_EN
Reserved
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Attribute Bits Attribute Encoding
FALSE
TRUE
8:0
1
4:0
2
FALSE
TRUE
13:0
FALSE
TRUE
14:0
DRP Binary
Encoding
0
1
10000
00000
0
1
0
1
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