Xilinx Virtex-6 FPGA User Manual page 104

Chapter 2: Shared Transceiver Features
X-Ref Target - Figure 2-2
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104
MGTREFCLK0[P/N]
MGTREFCLK1[P/N]
PERFCLK
GREFCLK
Q
(n+1)
Q
(n)
MGTREFCLK0[P/N]
MGTREFCLK1[P/N]
PERFCLK
GREFCLK
Q
(n-1)
MGTREFCLK0[P/N]
MGTREFCLK1[P/N]
PERFCLK
GREFCLK
Figure 2-2: Conceptual View of GTX Transceiver Reference Clocking
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1 0
Controlled
by Software
0
1 0
Controlled
by Software
0
Virtex-6 FPGA GTX Transceivers User Guide
TX PLL
CAS_CLK
RX PLL
NA
GTX0
TX PLL
CAS_CLK
1
RX PLL
NA
GTX3
GTX2
GTX1
TX PLL
CAS_CLK
RX PLL
NA
GTX0
TX PLL
CAS_CLK
1
RX PLL
NA
GTX3
UG366_c2_01_051509
UG366 (v2.5) January 17, 2011