Xilinx Virtex-6 FPGA User Manual page 305

Table B-1: Attributes DRP Address Map (Cont'd)
DADDR DRP Bits R/W
15:12
11
R/W
Bh
10
9:0
15:14
13 R/W
Ch
12:0
15
14 R/W
Dh
13:10
9:0
15
R/W
Eh
14:10
9:0
15:10
Fh R/W
9:0
15:10
R/W
10h
9:0
15
14 R/W
11h
13:10
9:0
15
14
13:12
R/W
12h
11:10
9:0
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Attribute Name
RX_IDLE_HI_CNT
RX_XCLK_SEL
RX_EN_IDLE_RESET_BUF
CHAN_BOND_SEQ_2_4
Reserved
RX_FIFO_ADDR_MODE
Reserved
CLK_COR_PRECEDENCE
CLK_CORRECT_USE
CLK_COR_SEQ_1_ENABLE
CLK_COR_SEQ_1_1
CLK_COR_KEEP_IDLE
CLK_COR_REPEAT_WAIT
CLK_COR_SEQ_1_2
CLK_COR_MIN_LAT
CLK_COR_SEQ_1_3
CLK_COR_MAX_LAT
CLK_COR_SEQ_1_4
CLK_COR_INSERT_IDLE_FLAG
CLK_COR_SEQ_2_USE
CLK_COR_SEQ_2_ENABLE
CLK_COR_SEQ_2_1
Reserved
SHOW_REALIGN_COMMA
RX_SLIDE_MODE
CLK_COR_ADJ_LEN
CLK_COR_SEQ_2_2
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Attribute Bits Attribute Encoding
3:0 0-15
RXREC
RXUSR
FALSE
TRUE
9:0 0-1023
1:0
FALSE
TRUE
12:0
FALSE
TRUE
FALSE
TRUE
3:0 0-15
9:0 0-1023
FALSE
TRUE
4:0 0-31
9:0 0-1023
5:0 3-48
9:0 0-1023
5:0 3-48
9:0 0-1023
FALSE
TRUE
FALSE
TRUE
3:0 0-15
9:0 0-1023
FALSE
TRUE
OFF
AUTO
1:0
PCS
PMA
1
2
1:0
Reserved
4
9:0 0-1023
DRP Binary
Encoding
(1)
1
0
1
0
1
(1)
1
0
1
0
1
0
1
(1)
1
(1)
1
0
1
(1)
1
(1)
1
(1)
1
(1)
1
(1)
1
(1)
1
0
1
0
1
(1)
1
(1)
1
0
1
00
01
10
11
00
01
11
(1)
1
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