Xilinx Virtex-6 FPGA User Manual page 175

Table 3-31: TX Configurable Driver Ports (Cont'd)
Port
TXPDOWNASYNCH
TXPOSTEMPHASIS[4:0]
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Dir Clock Domain
In Async Determines if TXELECIDLE and TXPOWERDOWN should be
treated as synchronous or asynchronous signals. Enables
compliance during cold and warm PCI Express resets.
In Async Transmitter Post-Cursor TX Pre-Emphasis Control. The default is
user specified. All listed values (dB) are typical.
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Description
0: Sets TXELECIDLE and TXPOWERDOWN to synchronous
mode.
1: Sets TXELECIDLE and TXPOWERDOWN to asynchronous
mode.
[4:0] dB (Post-Emphasis Magnitude)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
TX Configurable Driver
0.18
0.19
0.18
0.18
0.18
0.18
0.18
0.18
0.19
0.2
0.39
0.63
0.82
1.07
1.32
1.6
1.65
1.94
2.21
2.52
2.76
3.08
3.41
3.77
3.97
4.36
4.73
5.16
5.47
5.93
6.38
6.89
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