Xilinx Virtex-6 FPGA User Manual page 103

document describes the reference clocking architecture of the Virtex-6 FPGA GTX
transceivers.
Reference clock features include:
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Figure 2-2
reference clock pin pairs, and dedicated north/south reference clock routing. Each GTX
transceiver in a Quad has seven clock inputs available:
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Clock routing for north and south bound clocks.
Clock inputs available per GTX PLL.
Static or dynamic selection of the reference clock for the transmitter and receiver
PLLs.
shows the Quad architecture with four GTX transceivers, two dedicated
Two local reference clock pin pairs, MGTREFCLK[0/1]
Two reference clock pin pairs from the Quads above, SOUTHREFCLK[0/1]
Two reference clocks pin pairs or below, NORTHREFCLK[0/1]
Internal to each GTX transceiver, the clock from the receiver can be forwarded to the
transmit PLL reference clock, CAS_CLK. CAS_CLK must only be used for diagnostics
purposes.
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Reference Clock Selection
103