Xilinx Virtex-6 FPGA User Manual page 4

Date Version
08/11/09 2.0
(Cont'd)
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
Chapter 3 (Cont'd):
• Changed the widths of TXPREEMPHASIS, TXDIFFCTRL, and TXPOSTEMPHASIS in
Figure 3-31, page 173.
• Revised description of RXPOWERDOWN and TXPOWERDOWN in
• Added note to the Functional Description of
• In Table 3-34, page 181, changed TXELECIDLE to one bit and added COMFINISH.
• Updated descriptions of TXELECIDLE and TXPOWERDOWN ports in
page 181
Chapter 4:
• Added new sections GTX RX Reset in Response to Completion of Configuration, page
GTX RX Reset in Response to GTXRXRESET Pulse, page
page 264, GTX RX Component-Level Resets, page
page 266, After Turning on a Reference Clock to RX PLL, page
Reference Clock to RX PLL, page
page 267, RX Rate Change with RX Elastic Buffer Enabled, page
RX Elastic Buffer Bypassed, page
Remote Power-Up, page
page 268, After an RX Elastic Buffer Error, page
After Changing Channel Bonding Mode on the Fly, page
After an Oversampler Error, page
• Added ESD Diodes label to
page 188, Figure 4-5, page
• Revised captions for Figure 4-9, page 194
• In Table 4-2, page 185, added sentence about system evaluation purposes to the
descriptions of TERMINATION_CTRL[4:0] and TERMINATION_OVRD.
• Added GATERXELECIDLE and IGNORESIGDET ports to
• Added Figure 4-8, page
• In Serial Clock Divider, page
line rate and multiple line rate applications.
• In Table 4-23, page 208, removed RXPLL_DIVSEL_OUT = Ignored from all rows in the
Dynamic Control via Ports column.
• In Table 4-24, page 209, revised the clock domain and description of RXRATEDONE.
• In Table 4-25, page 209, revised the description of TRANS_TIME_RATE.
• Added RX decoder port and attribute tables
respectively).
• Changed description of RXDLYALIGNMONITOR[7:0] to reserved in
• Moved description of RX CDR lock to
• Revised descriptions of CLK_COR_ADJ_LEN, CLK_COR_DET_LEN,
CLK_COR_MAX_LAT, and CLK_CORRECT_USE attributes in
• In the Functional Description of
Added Figure 4-49, page 261
• In Table 4-52, page 261, revised the GTXTEST[12:0] description and added the
PRBSCNTRESET port.
• Added the RX_EN_REALIGN_RESET_BUF2 attribute to
• Revised "GTX Lanes in Channel" values for 2-byte and 4-byte rows in
Appendix B:
• Added new appendix.
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Revision
TX Out-of-Band Signaling, page
264,
267, After Assertion/Deassertion of RXPOWERDOWN,
267, RX Parallel Clock Source Reset, page
267, Electrical Idle Reset, page
268,
268, and After Comma Realignment, page
Figure 4-2, page 184, Figure 4-3, page
189, Figure 4-6, page 190, and
and Figure 4-10, page
193.
208, provided more details on using the D divider in fixed
(Table 4-38, page 230
RX CDR, page
RX Initialization, page
showing the GTX receiver reset hierarchy.
Table 3-33, page
180.
Table 3-34,
263, Link Idle Reset Support,
After Power-up and Configuration,
266, After Changing the
267, RX Rate Change with
267,
267, After Connecting RXN/RXP,
Before Channel Bonding, page
268, After a PRBS Error, page
269.
187, Figure 4-4,
Figure 4-7, page 191.
195.
Table 4-9, page 192.
and Table 4-39, page
Table 4-40, page
204.
Table 4-47, page
261, revised #2 and added #3.
Table 4-53, page 262.
Table 4-58, page
UG366 (v2.5) January 17, 2011
179.
263,
After
268,
268,
231,
233.
242.
270.