Xilinx Virtex-6 FPGA User Manual page 99

X-Ref Target - Figure 1-62
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
MGTRXP3_101
MGTRXN3_101
MGTTXP3_101
MGTTXN3_101
MGTRXP2_101
MGTRXN2_101
MGTTXP2_101
MGTTXN2_101
MGTREFCLK1P_101
MGTREFCLK1N_101
MGTREFCLK0P_101
MGTREFCLK0N_101
MGTRXP1_101
MGTRXN1_101
MGTTXP1_101
MGTTXN1_101
MGTRXP0_101
MGTRXN0_101
MGTTXP0_101
MGTTXN0_101
Figure 1-62: Placement Diagram for the FF1924 Package (11 of 12)
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Left Edge of the Die
AP40
AP39
HX380T:GTXE1_X0Y7
HX565T:GTXE1_X0Y7
AP44
AP43
AT40
AT39
HX380T:GTXE1_X0Y6
HX565T:GTXE1_X0Y6
AR42
AR41
AR37
AR38
AU37
AU38
AV40
AV39
HX380T:GTXE1_X0Y5
HX565T:GTXE1_X0Y5
AT44
AT43
AY40
AY39
HX380T:GTXE1_X0Y4
HX565T:GTXE1_X0Y4
AU42
AU41
Implementation
QUAD_101
UG366_c1_62_111110
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