Xilinx Virtex-6 FPGA User Manual page 21

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Figure 1-2
FPGA.
X-Ref Target - Figure 1-2
GTX transceivers are clustered together in a set of four called a Quad or Q.
illustrates the clustering of four GTX transceivers to a Quad. Refer to
page 41
Quad.
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
The Virtex-6 FPGA Configuration User Guide provides more information on the
Configuration and Clock, MMCM, and I/O blocks.
The Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide provides detailed
information on the Ethernet MAC.
illustrates the location of the GTX transceiver inside the Virtex-6 XC6VLX75T
I/O I/O
Column Column
Figure 1-2: GTX Transceiver Inside the Virtex-6 XC6VLX75T FPGA
for placement information and the mapping of each transceiver into a specific
www.xilinx.com
Virtex-6 FPGA (XC6VLX75T)
MMCM
I/O
MMCM
Column
MMCM
Overview
GTXE1
Column
GTXE1_
X0Y11
Ethernet
GTXE1_
MAC
X0Y10
Ethernet
GTXE1_
MAC
X0Y9
GTXE1_
X0Y8
GTXE1_
X0Y7
GTXE1_
X0Y6
GTXE1_
Integrated
X0Y5
Block for
PCI Express
GTXE1_
Operation
X0Y4
GTXE1_
X0Y3
GTXE1_
X0Y2
Ethernet
GTXE1_
MAC X0Y1
GTXE1_
Ethernet
MAC X0Y0
UG366_c1_02_051509
Figure 1-3
Implementation,
21