Xilinx Virtex-6 FPGA User Manual page 109

X-Ref Target - Figure 2-5
Note:
floating, and the input port CEB is set to logic 0.
The Xilinx implementation tools make the necessary adjustments to the north/south
routing shown in
route clocks from one Quad to another when required.
The following rules must be observed when sharing a reference clock to ensure that jitter
margins for high-speed designs are met:
1.
2.
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
IBUFDS_GTXE1
MGTREFCLKP
MGTREFCLKN
Figure 2-5: Multiple GTX Transceivers with Shared Reference Clock
The IBUFDS_GTXE1 diagram in
Figure 2-2 as well as pin swapping necessary to the GTX clock inputs to
The number of Quads above the sourcing Quad must not exceed one.
The number of Quads below the sourcing Quad must not exceed one.
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Q
(n+1)
Q
(n)
I
O
IB
Q
(n–1)
Figure 2-5 is a simplification. The output port ODIV2 is left
Reference Clock Selection
GTXE1
MGTREFCLKTX[0]
MGTREFCLKRX[0]
GTXE1
MGTREFCLKTX[0]
MGTREFCLKRX[0]
GTXE1
MGTREFCLKTX[0]
MGTREFCLKRX[0]
GTXE1
MGTREFCLKTX[0]
MGTREFCLKRX[0]
GTXE1
MGTREFCLKTX[0]
MGTREFCLKRX[0]
GTXE1
MGTREFCLKTX[0]
MGTREFCLKRX[0]
GTXE1
MGTREFCLKTX[0]
MGTREFCLKRX[0]
GTXE1
MGTREFCLKTX[0]
MGTREFCLKRX[0]
GTXE1
MGTREFCLKTX[0]
MGTREFCLKRX[0]
GTXE1
MGTREFCLKTX[0]
MGTREFCLKRX[0]
GTXE1
MGTREFCLKTX[0]
MGTREFCLKRX[0]
GTXE1
MGTREFCLKTX[0]
MGTREFCLKRX[0]
UG366_c2_04_071009
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