Xilinx Virtex-6 FPGA User Manual page 311

Table B-1: Attributes DRP Address Map (Cont'd)
DADDR DRP Bits R/W
15
14:12 R/W
27h
11:6
5:0
15
14:12
R/W
28h
11:6
5:0
15:12
11:6 R/W
29h
5:0
15:9
8 R/W
2Ah
7:0
15:12
11
10 R/W
2Bh
9
8:0
15:0 R/W
2Ch
15:8
R/W
2Dh
7:0
15:11
10:9
8
7 R/W
2Eh
6
5
4:0
15
14
R/W
2Fh
13:11
10
9:0
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Attribute Name
TX_EN_RATE_RESET_BUF
SATA_IDLE_VAL
SATA_MIN_INIT
SATA_MAX_INIT
Reserved
SATA_BURST_VAL
SATA_MIN_BURST
SATA_MAX_BURST
Reserved
SAS_MIN_COMSAS
SAS_MAX_COMSAS
Reserved
RXPRBSERR_LOOPBACK
Reserved
Reserved
RX_EN_IDLE_HOLD_DFE
RX_EN_IDLE_RESET_FR
RX_EN_IDLE_HOLD_CDR
Reserved
Reserved
RX_EYE_OFFSET
DFE_CFG
DFE_CAL_TIME
RX_EYE_SCANMODE
RCV_TERM_VTTRX
RCV_TERM_GND
TERMINATION_OVRD
Reserved
TERMINATION_CTRL
TXGEARBOX_USE
TX_XCLK_SEL
TX_IDLE_ASSERT_DELAY
COMMA_DOUBLE
COMMA_10B_ENABLE
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Attribute Bits Attribute Encoding
FALSE
TRUE
2:0 0-7
5:0 1-61
5:0 1-61
2:0 0-7
5:0 1-61
5:0 1-61
3:0
5:0 1-61
5:0 1-61
6:0
0-1
7:0
3:0
FALSE
TRUE
FALSE
TRUE
FALSE
TRUE
8:0
15:0
7:0
7:0 0-255
4:0 0-31
1:0 0-3
FALSE
TRUE
FALSE
TRUE
FALSE
TRUE
4:0 0-31
FALSE
TRUE
TXUSR
TXOUT
2:0 0-7
FALSE
TRUE
9:0 0-1023
DRP Binary
Encoding
0
1
(1)
1
(1)
1
(1)
1
(1)
1
(1)
1
(1)
1
(1)
1
(1)
1
(1)
1
0
1
0
1
0
1
(1)
1
(1)
1
(1)
1
0
1
0
1
0
1
(1)
1
0
1
1
0
(1)
1
0
1
(1)
1
311