Xilinx Virtex-6 FPGA User Manual page 112

Chapter 2: Shared Transceiver Features
The flexibility of the reference clock selection architecture allows each transceiver within a
Quad to have access to the dedicated reference clocks from the Quad immediately above
and below.
quad can access the dedicated reference clocks from another Quad by using the
NORTHREFCLK and SOUTHREFCLK ports. The Xilinx software tools handle the
complexity of the multiplexers and associated routing for designs that require a single
reference clock per GTX transceiver PLL. In situations where there is more than one
reference clock option per GTX transceiver PLL
connect the corresponding ports and set TXPLLREFSELDY[2:0] and
RXPLLREFSELDY[2:0] based on the design requirements.
X-Ref Target - Figure 2-7
Note:
floating, and the input port CEB is set to logic 0.
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112
Figure 2-7 shows an example of how one of the transceivers belonging to one
IBUFDS_GTXE1
MGTREFCLK0P
MGTREFCLK0N
IBUFDS_GTXE1
MGTREFCLK1P
MGTREFCLK1N
IBUFDS_GTXE1
MGTREFCLK0P
MGTREFCLK0N
IBUFDS_GTXE1
MGTREFCLK1P
MGTREFCLK1N
Figure 2-7: Multiple GTX Transceivers with Multiple Reference Clocks in Different
The IBUFDS_GTXE1 diagram in
www.xilinx.com
(Figure
I
O
IB
I
O
IB
I
O
IB
I
O
IB
Quads
Figure 2-6 is a simplification. The output port ODIV2 is left
Virtex-6 FPGA GTX Transceivers User Guide
2-7), the user design is required to
Q
(n)
GTXE1
SOUTHREFCLKTX[0]
SOUTHREFCLKRX[0]
SOUTHREFCLKTX[1]
SOUTHREFCLKRX[1]
MGTREFCLKTX[0]
MGTREFCLKRX[0]
MGTREFCLKTX[1]
MGTREFCLKRX[1]
NORTHREFCLKTX[0]
NORTHREFCLKRX[0]
NORTHREFCLKTX[1]
NORTHREFCLKRX[1]
Q
(n+1)
GTXE1
SOUTHREFCLKTX[0]
SOUTHREFCLKRX[0]
SOUTHREFCLKTX[1]
SOUTHREFCLKRX[1]
MGTREFCLKTX[0]
MGTREFCLKRX[0]
MGTREFCLKTX[1]
MGTREFCLKRX[1]
NORTHREFCLKTX[0]
NORTHREFCLKRX[0]
NORTHREFCLKTX[1]
NORTHREFCLKRX[1]
UG366_c2_09_061409
UG366 (v2.5) January 17, 2011