Xilinx Virtex-6 FPGA User Manual page 259

X-Ref Target - Figure 4-47
LOCK_INIT
block_lock <= false
test_sh <= false
Unconditional Transition
RESET_CNT
sh_cnt <= 0
sh_invalid_cnt <= 0
slip_done <= false
test_sh = 1
TEST_SH
test_sh <= false
test_sh = true AND
sh_cnt < 64
sh_valid = 1
VALID_SH
sh_cnt <= sh_cnt + 1
sh_cnt = 64 AND
sh_invalid_cnt = 0
64_GOOD
block_lock <= true
Unconditional Transition
The state machine works by keeping track of valid and invalid synchronization headers.
Upon reset, block lock is deasserted, and the state is LOCK_INIT. The next state is
RESET_CNT where all counters are zeroed out. The synchronization header is analyzed in
the TEST_SH state. If the header is valid, sh_cnt is incremented in the VALID_SH state,
otherwise sh_count and sh_invalid_count are incremented in the INVALID_SH state.
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
sh_valid = 0
sh_cnt = 64 AND
sh_invalid_cnt > 0
Figure 4-47: Block Synchronization State Machine
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INVALID_SH
sh_cnt <= sh_cnt + 1
sh_invalid_cnt <= sh_invalid_cnt + 1
sh_cnt = 64 AND
sh_invalid_cnt < 16 AND
block_lock = true
sh_invalid_cnt = 16 OR
block_lock = false
SLIP
block_lock <= false
SLIP <= true
slip_done = true
RX Gearbox
test_sh = true AND
sh_cnt < 64 AND
sh_invalid_cnt < 16 AND
block_lock = true
UG366_c4_44_051509
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