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Xilinx Virtex-6 FPGA User Manual page 27

Gtx transceivers
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Table 1-1: Port and Attribute Summary (Cont'd)
TX Pattern Generator
TX Oversampling
TX Polarity Control
TX Fabric Clock Output Control
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Port/Attribute
Ports:
•
TXDLYALIGNDISABLE
•
TXDLYALIGNMONENB
•
TXDLYALIGNMONITOR[7:0]
•
TXDLYALIGNOVERRIDE
•
TXDLYALIGNRESET
•
TXDLYALIGNUPDSW
•
TXENPMAPHASEALIGN
•
TXOUTCLK
•
TXPLLLKDET
•
TXPLLLKDETEN
•
TXPMASETPHASE
•
TXUSRCLK
Attributes:
•
TX_BUFFER_USE
•
TX_BYTECLK_CFG[5:0]
•
TX_DATA_WIDTH
•
TX_DLYALIGN_CTRINC
•
TX_DLYALIGN_LPFINC
•
TX_DLYALIGN_MONSEL
•
TX_DLYALIGN_OVRDSETTING
•
TX_PMADATA_OPT
•
TX_XCLK_SEL
•
TXOUTCLK_CTRL
Ports:
•
TXENPRBSTST[2:0]
•
TXPRBSFORCEERR
Attributes:
•
RXPRBSERR_LOOPBACK
Attributes:
•
TX_OVERSAMPLE_MODE
Ports:
•
TXPOLARITY
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Port and Attribute Summary
Section, Page
page 155
page 155
page 155
page 155
page 155
page 155
page 156
page 156
page 156
page 156
page 156
page 156
page 157
page 157
page 157
page 157
page 157
page 157
page 157
page 157
page 158
page 158
page 164
page 164
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page 166
page 166
27

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