Xilinx Virtex-6 FPGA User Manual page 26

Chapter 1: Transceiver and Tool Overview
Table 1-1: Port and Attribute Summary (Cont'd)
TX Initialization
TX Encoder
TX Gearbox
TX Buffer
TX Buffer Bypass
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Port/Attribute
Ports:
• GTXTEST[12:0]
• GTXTXRESET
• PLLTXRESET
• TSTIN[19:0]
• TXDLYALIGNRESET
• TXRESET
• TXRESETDONE
Attributes:
• TX_EN_RATE_RESET_BUF
Ports:
• TXBYPASS8B10B[3:0]
• TXCHARDISPMODE[3:0]
• TXCHARDISPVAL[3:0]
• TXCHARISK[3:0]
• TXENC8B10BUSE
• TXKERR[3:0]
• TXRUNDISP[3:0]
Ports:
• TXGEARBOXREADY
• TXHEADER[2:0]
• TXSEQUENCE[6:0]
• TXSTARTSEQ
Attributes:
• GEARBOX_ENDEC
• TXGEARBOX_USE
Ports:
• TXBUFSTATUS[1:0]
• TXRESET
Attributes:
• TX_BUFFER_USE
• TX_OVERSAMPLE_MODE
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011