Xilinx Virtex-6 FPGA User Manual page 304

Appendix B: DRP Address Map of the GTX Transceiver
Table B-1: Attributes DRP Address Map (Cont'd)
DADDR DRP Bits R/W
15:13
R/W
6h
12:10
9:0
15:12
11:10 R/W
7h
9:0
15
14 R/W
8h
13:10
9:0
15
14 R/W
9h
13:10
9:0
15
14 R/W
Ah
13:10
9:0
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304
Attribute Name
RX_LOS_INVALID_INCR
RX_LOS_THRESHOLD
CHAN_BOND_SEQ_1_3
RX_IDLE_LO_CNT
CHAN_BOND_SEQ_LEN
CHAN_BOND_SEQ_1_4
RX_EN_RATE_RESET_BUF
RX_EN_REALIGN_RESET_BUF
CHAN_BOND_SEQ_2_ENABLE
CHAN_BOND_SEQ_2_1
RX_EN_MODE_RESET_BUF
CHAN_BOND_KEEP_ALIGN
CHAN_BOND_2_MAX_SKEW
CHAN_BOND_SEQ_2_2
RX_EN_IDLE_RESET_PH
CHAN_BOND_SEQ_2_USE
CHAN_BOND_SEQ_2_CFG
CHAN_BOND_SEQ_2_3
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Attribute Bits Attribute Encoding
1
2
4
8
2:0
16
32
64
128
4
8
16
32
2:0
64
128
256
512
9:0 0-1023
3:0 0-15
1
2
1:0
Reserved
4
9:0 0-1023
FALSE
TRUE
FALSE
TRUE
3:0 0-15
9:0 0-1023
FALSE
TRUE
FALSE
TRUE
3:0 1-14
9:0 0-1023
FALSE
TRUE
FALSE
TRUE
3:0 <4:0> 0-31
9:0 0-1023
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
DRP Binary
Encoding
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
(1)
1
(1)
1
00
01
11
(1)
1
0
1
0
1
(1)
1
(1)
1
0
1
0
1
(1)
1
(1)
1
0
1
0
1
(1)
1
(1)
1