Xilinx Virtex-6 FPGA User Manual page 272

Chapter 4: Receiver
Table 4-60: FPGA RX Ports (Cont'd)
Port
RXUSRCLK
RXUSRCLK2
Table 4-61
Table 4-61: FPGA RX Attributes
Attribute
GEN_RXUSRCLK
RX_DATA_WIDTH
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272
Dir Clock Domain
In Clock This port provides a clock for the internal RX PCS datapath. In
some use cases, this clock is internally generated. See
In Clock This port synchronizes the FPGA logic with the RX interface.
This clock must be positive-edge aligned to RXUSRCLK when
RXUSRCLK is provided by the user.
defines the FPGA RX attributes.
Type
Boolean Controls internal generation of RXUSRCLK available in certain modes of
operation. See
TRUE: RXUSRCLK internally generated. RXUSRCLK must be tied Low.
FALSE: RXUSRCLK must be provided by user.
Integer Sets the bit width of the RXDATA port. When 8B/10B decoding is enabled,
RX_DATA _WIDTH must be set to 10, 20, or 40. Valid settings are 8, 10, 16, 20,
32, and 40.
See Interface Width Configuration, page 269
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Description
Description
RXUSRCLK and RXUSRCLK2 Generation, page
Virtex-6 FPGA GTX Transceivers User Guide
Table 4-58.
270.
for more details.
UG366 (v2.5) January 17, 2011