Xilinx Virtex-6 FPGA User Manual page 308

Appendix B: DRP Address Map of the GTX Transceiver
Table B-1: Attributes DRP Address Map (Cont'd)
DADDR DRP Bits R/W
15:4
3 R/W
18h
2:0
15:0 R/W
19h
15:8
R/W
1Ah
7:0
15:14
13:11
10:7
R/W
1Bh
6
5:1
0
15
14:6
1Ch R/W
5:1
0
15:0 R/W
1Dh
15:8
R/W
1Eh
7:0
15:14
13:11
10:9
8
R/W
1Fh
7
6
5:1
0
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308
Attribute Name
Reserved
RXGEARBOX_USE
GEARBOX_ENDEC
RXPLL_COM_CFG
RXPLL_CP_CFG
RXPLL_COM_CFG
RXPLL_DIVSEL_OUT
RXPLL_LKDET_CFG
Reserved
RXPLL_DIVSEL45_FB
RXPLL_DIVSEL_FB
Reserved
RX_OVERSAMPLE_MODE
Reserved
RXPLL_DIVSEL_REF
Reserved
TXPLL_COM_CFG
TXPLL_CP_CFG
TXPLL_COM_CFG
TXPLL_DIVSEL_OUT
TXPLL_LKDET_CFG
Reserved
TX_CLK_SOURCE
Reserved
TXPLL_DIVSEL45_FB
TXPLL_DIVSEL_FB
Reserved
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Attribute Bits Attribute Encoding
11:0
FALSE
TRUE
2:0 0-7
15:0
7:0
23:16
1
1:0 2
4
2:0 0-7
3:0
5
4
2
4:0 4
5
FALSE
TRUE
8:0
1
4:0
2
15:0
7:0
23:16
1
1:0 2
4
2:0 0-7
1:0
RXPLL
TXPLL
5
4
2
4:0 4
5
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
DRP Binary
Encoding
0
1
(1)
1
00
01
10
(1)
1
1
0
00000
00010
00011
0
1
10000
00000
00
01
10
(1)
1
1
0
1
0
00000
00010
00011