Xilinx Virtex-6 FPGA User Manual page 310

Appendix B: DRP Address Map of the GTX Transceiver
Table B-1: Attributes DRP Address Map (Cont'd)
DADDR DRP Bits R/W
15
14:10 R/W
23h
9:0
15:12
R/W
24h
11:0
15
14:10
R/W
25h
9:8
7:0
15:14
13:12
R/W
26h
11:6
5:0
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310
Attribute Name
Reserved
TX_CLK25_DIVIDER
TRANS_TIME_TO_P2
COM_BURST_VAL
TRANS_TIME_FROM_P2
TX_PMADATA_OPT
Reserved
CM_TRIM
TRANS_TIME_NON_P2
BGTEST_CFG
TXPLL_SATA
SATA_MIN_WAKE
SATA_MAX_WAKE
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Attribute Bits Attribute Encoding
6
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
4:0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
9:0
3:0 0-15
11:0
0-1
4:0
1:0 0-3
7:0
1:0 0-3
1:0 0-3
5:0 1-61
5:0 1-61
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
DRP Binary
Encoding
00101
00000
00001
00010
00011
00100
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
(1)
1
(1)
1
(1)
1
(1)
1
(1)
1
(1)
1
(1)
1