Rx Analog Front End - Xilinx Virtex UltraScale+ FPGAs User Manual

11. RX FEC

RX Analog Front End

The RX analog front end (AFE) is an ADC-based input differential buffer. It has the following
features:
• Configurable RX termination voltage
• Calibrated termination resistors
Board
~100 nF
~100 nF
Ports and Attributes
The following table defines the RX AFE ports.
Table 48: RX AFE ports
Ports
CH[0/1]_GTMRXP,
CH[0/1]_GTMRXN
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
RX Analog Front End
Figure 37:
UltraScale Device
ACJTAG RX
MGTAVTT
50Ω
PAD_RTERM_VCOM_MODE
50Ω
MGTAVTT
MGTAVTT
ACJTAG RX
Dir
In (Pad)
PAD_RTERM_VCOM_LVL
+ +
Programmable
– –
FLOAT
Clock Domain
RX Serial Clock Differential complements of one another
forming a differential receiver input pair.
These ports represent pads. The location
of these ports must be constrained (see
Implementation) and brought to the top
level of the design.
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Chapter 4: Receiver
X20922-111918
Description
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