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Xilinx Virtex-6 FPGA User Manual page 25

Gtx transceivers
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Table 1-1: Port and Attribute Summary (Cont'd)
Loopback
DRP
FPGA TX Interface
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Port/Attribute
Attributes:
•
BGTEST_CFG
•
BIAS_CFG
•
PMA_TX_CFG
•
POWER_SAVE
•
TRANS_TIME_FROM_P2
•
TRANS_TIME_NON_P2
•
TRANS_TIME_RATE
•
TRANS_TIME_TO_P2
Ports:
•
LOOPBACK[2:0]
Attributes:
•
TXDRIVE_LOOPBACK_HIZ
•
TXDRIVE_LOOPBACK_PD
Ports:
•
DADDR[7:0]
•
DCLK
•
DEN
•
DI[15:0]
•
DRPDO[15:0]
•
DRDY
•
DWE
Ports:
•
MGTREFCLKFAB[1:0]
•
TXCHARDISPMODE[3:0]
•
TXCHARDISPVAL[3:0]
•
TXDATA[31:0]
•
TXUSRCLK
•
TXUSRCLK2
Attributes:
•
GEN_TXUSRCLK
•
TX_DATA_WIDTH
www.xilinx.com
Port and Attribute Summary
Section, Page
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