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Xilinx Virtex-6 FPGA User Manual page 221

Gtx transceivers
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RX Byte and Word Alignment
X-Ref Target - Figure 4-27
RXUSRCLK2
RXSLIDE
Slide Results on RXDATA
After Several Cycles of Latency
RXDATA
00000000000000010000
00000000000000100000
00000000000001000000
TXDATA
00000000000000010000
UG366_c4_27_103010
Figure 4-27: Manual Data Alignment Using RXSLIDE for RX_DATA_WIDTH = 20 Bits
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
www.xilinx.com
221
UG366 (v2.5) January 17, 2011

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