Xilinx Virtex-6 FPGA User Manual page 292

Chapter 5: Board Design Guidelines
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Eliminate routing of GTX transceiver signals and SelectIO interface signals on
adjacent layers. Be aware of the potential of broadside coupling if these signals are
routed on adjacent layers.
Maintain isolation of the return current paths for both the SelectIO interface signals
and the GTX transceiver signals including both traces and vias.
The power islands for the GTX transceivers are also a potential source for SelectIO
interface induced noise. SelectO interface signals should not be routed over the GTX
power islands.
www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011