Xilinx Virtex-6 FPGA User Manual page 174

Chapter 3: Transmitter
Table 3-31: TX Configurable Driver Ports (Cont'd)
Port
TXDIFFCTRL[3:0]
TXELECIDLE
TXINHIBIT
TXMARGIN[2:0]
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174
Dir Clock Domain
In Async Driver Swing Control. The default is user specified. All listed
values (mV
In TXUSRCLK2, TXPDOWNASYNCH makes this pin asynchronous.
Async
In TXUSRCLK2 When High, this signal blocks transmission of TXDATA and
forces TXP to 0 and TXN to 1.
In Async TX Margin control for PCI Express PIPE Interface
are mapped internally to TXDIFFCTRL/TXBUFDIFFCTRL via
attributes.
[2:0]
000
001
010
011
100
101
110
111
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Description
) are typical.
PPD
[3:0] mV
PPD
110
0000
210
0001
310
0010
400
0011
480
0100
570
0101
660
0110
740
0111
810
1000
880
1001
940
1010
990
1011
1040
1100
1080
1101
1110
1110
1130
1111
Full Range Half Range
800-1200 400-1200
800-1200 400-700
800-1200 400-700
200-400 100-200
100-200 100-200
default to "DIRECT" mode
Virtex-6 FPGA GTX Transceivers User Guide
(1)
. These signals
Full Range Half Range
Attribute Attribute
TX_MARGIN_ TX_MARGIN_
FULL_0 LOW_0
TX_MARGIN_ TX_MARGIN_
FULL_1 LOW_1
TX_MARGIN_ TX_MARGIN_
FULL_2 LOW_2
TX_MARGIN_ TX_MARGIN_
FULL_3 LOW_3
TX_MARGIN_ TX_MARGIN_
FULL_4 LOW_4
UG366 (v2.5) January 17, 2011