Xilinx Virtex-6 FPGA User Manual page 312

Appendix B: DRP Address Map of the GTX Transceiver
Table B-1: Attributes DRP Address Map (Cont'd)
DADDR DRP Bits R/W
15:14
13:11
R/W
30h
10
9:0
15
14:12
R/W
31h
11
10
9:0
15:0 R/W
32h
15:0 R/W
33h
15:0 R/W
34h
15:0 R/W
35h
15:4
R/W
36h
3:0
15:0 R/W
37h
15:14
13:7 R/W
38h
6:0
15:14
13:7 R/W
39h
6:0
15
14
3Ah
13:7 R/W
6:0
15:14
13:7
3Bh
6:0
15
14 R/W
3Ch
13:7
6:0
3Dh 15:0 R/W
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312
Attribute Name
Reserved
TX_IDLE_DEASSERT_DELAY
MCOMMA_DETECT
MCOMMA_10B_VALUE
GEN_TXUSRCLK
TX_DATA_WIDTH
TX_BUFFER_USE
PCOMMA_DETECT
PCOMMA_10B_VALUE
PMA_CFG
PMA_CFG
PMA_CFG
PMA_CFG
PMA_CFG
PMA_TX_CFG
PMA_TX_CFG
Reserved
TX_MARGIN_FULL_0
TX_MARGIN_LOW_0
TX_TDCC_CFG
TX_MARGIN_FULL_1
TX_MARGIN_LOW_1
TXDRIVE_LOOPBACK_PD
TXDRIVE_LOOPBACK_HIZ
TX_MARGIN_FULL_2
TX_MARGIN_LOW_2
Reserved
TX_MARGIN_FULL_3
TX_MARGIN_LOW_3
TX_DRIVE_MODE
Reserved
TX_MARGIN_FULL_4
TX_MARGIN_LOW_4
Reserved
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Attribute Bits Attribute Encoding
1:0
2:0 0-7
FALSE
TRUE
9:0 0-1023
FALSE
TRUE
20
8
10
2:0
16
32
40
FALSE
TRUE
FALSE
TRUE
9:0 0-1023
15:0
31:16
47:32
63:48
75:64
19:16
15:0
1:0
6:0 0-127
6:0 0-127
1:0 0-3
6:0 0-127
6:0 0-127
FALSE
TRUE
FALSE
TRUE
6:0 0-127
6:0 0-127
1:0
6:0 0-127
6:0 0-127
DIRECT
PIPE
6:0 0-127
6:0 0-127
15:0
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
DRP Binary
Encoding
(1)
1
0
1
(1)
1
0
1
011
000
001
010
100
101
0
1
0
1
(1)
1
(1)
1
(1)
1
(1)
1
(1)
1
(1)
1
0
1
0
1
(1)
1
(1)
1
(1)
1
(1)
1
0
1
(1)
1
(1)
1