Xilinx Virtex-6 FPGA User Manual page 211

X-Ref Target - Figure 4-16
As illustrated in
region, user logic observes a corresponding increased in bit error rate on the received user
data.
X-Ref Target - Figure 4-17
This scan mode provides only the physical mechanism to offset the data sampling position.
It does not provide the actual scanning and bit error rate monitoring functionalities. These
functionalities need to be implemented in either FPGA user logic or user software. This
mode is only recommended for diagnostic purposes because the received user data is
corrupted due to the non-optimal sampling position.
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
RXP/N RXP/N
RXEQ RXEQ
DFE DFE
DFE DFE
Local Local
FSM FSM
REFCLK REFCLK
Figure 4-16: Horizontal Eye Margin Scan Detail
Figure 4-17, when the data sampling phase approaches the edge transition
BER
-6
1e
-8
1e
-10
1e
-12
1e
Figure 4-17: Data Sampling Position to Bit Error Rate
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Edge Edge
Sampler Sampler
PI (E) PI (E)
Data
Sampler
PI (D)
Scan Scan
Sampler Sampler
PI (S) PI (S)
E
D
0 0
RX_EYE_OFFSET
Internal Eye Opening
RX Margin Analysis
Demux
CDR FSM
RXDATA RXDATA
Demux
RX_EYE_OFFSET
RXRECCLK RXRECCLK
UG366_c4_15_051509
E
1
UG366_c4_16_051509
RX RX
PLL PLL
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