Xilinx Virtex-6 FPGA User Manual page 237

X-Ref Target - Figure 4-33
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Fail
Figure 4-33: Steps Required for Successful RX Phase Alignment
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RESET
Wait for MMCM Lock.
RXN/RXP Should be Driven.
Drive
RXENPMAPHASEALIGN
and Wait for 32
RXUSRCLK2 Cycles
Assert RXPMASETPHASE
for 32 RXUSRCLK2 Cycles
to Phase Align
Validate Data
Received at
Fabric Interface
Pass
Phase Alignment
Done
UG366_c4_30_122810
RX Buffer Bypass
237