Xilinx Virtex-6 FPGA User Manual page 187

X-Ref Target - Figure 4-3
Board
~100 nF
~100 nF
Table 4-5
shows the Use Mode 2 configuration.
Table 4-5: RX Termination Use Mode 2 Configuration and Notes
External
Use Mode AC
Voltage
Coupling
2 On
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
FPGA
MGTAVTT_*
ESD Diodes
nominal
50Ω
nominal
50Ω
MGTAVTT_*
ESD Diodes
Figure 4-3: RX Termination Use Mode 1 Configuration
outlines the recommended settings for RX termination in Use Mode 2.
Term Internal AC Internal
Coupling Bias
VTT Off 800 mV
www.xilinx.com
nominal 7 pF
GND
nominal 7 pF
Max
Swing Suggested Protocols and Usage Notes
mV
DPP
1200 Protocol: Backplane, CEI-6 (1200 mV
Wireless, Serial RapidIO, DisplayPort
(0.4V/0.6V/0.8V option).
Protocols such as HD-SDI and SD-SDI can also
use this termination mode if cable equalizer
devices are used between SDI cable and the
Xilinx FPGA SerDes interface. In this
configuration, the signal swing from the cable
equalizer device is usually less than 1200 mV.
Attribute Settings:
AC_CAP_DIS = TRUE
RCV_TERM_GND = FALSE
RCV_TERM_VTTRX = TRUE
RX Analog Front End
V
CM
nominal
2/3 MGTAVTT_*
50 KΩ
nominal
50 KΩ
UG366_c4_03_071009
Figure 4-4
),
DPP
187