Xilinx Virtex-6 FPGA User Manual page 118
Gtx transceivers
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Chapter 2: Shared Transceiver Features
Table 2-10: PLL Divider Settings for Common Protocols (Cont'd)
Line Rate
Standard
[Gb/s]
4.25
Fibre Channel
2.125
(Multi-Rate)
1.0625
XAUI
3.125
GigE
1.25
6.25
5
Aurora
3.125
(Single Rate)
2.5
1.25
6.25
5
Aurora
3.125
(Multi-Rate)
2.5
1.25
3.125
Serial RapidIO
2.5
(Single Rate)
1.25
3.125
Serial RapidIO
2.5
(Multi-Rate)
1.25
3
SATA
1.5
5
PCIe
Optimal Jitter
2.5
5
PCIe
100 MHz REFCLK
2.5
2.4576
CPRI 1-4X
1.2288
(Multi-Rate)
0.6144
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118
Internal Data
PLL Frequency
Width
[GHz]
[16b/20b]
20b
2.125
20b
2.125
20b
2.125
20b
1.5625
20b
2.5
20b
3.125
20b
2.5
20b
1.5625
20b
2.5
20b
1.25
20b
3.125
20b
2.5
20b
3.125
20b
2.5
20b
2.5
20b
1.5625
20b
2.5
20b
2.5
20b
1.5625
20b
2.5
20b
2.5
20b
1.5
20b
1.5
20b
2.5
20b
2.5
20b
2.5
20b
2.5
20b
1.2288
20b
1.2288
20b
1.2288
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Using Typical REFCLK
REFCLK
Frequency
(Typical)
[MHz]
N1
N2
212.5
5
2
212.5
5
2
212.5
5
2
156.25
5
2
125
5
4
312.5
5
2
250
5
2
156.25
5
2
125
5
4
125
5
2
312.5
5
2
312.5
4
2
312.5
5
2
312.5
4
2
312.5
4
2
156.25
5
2
125
5
4
125
5
4
156.25
5
2
156.25
4
4
156.25
4
4
150
5
2
150
5
2
250
5
2
125
5
4
100
5
5
100
5
5
122.88
5
2
122.88
2
5
122.88
2
5
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
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