Xilinx Virtex-6 FPGA User Manual page 290

Chapter 5: Board Design Guidelines
X-Ref Target - Figure 5-14
For signals that are on the inner rows of pins, it is necessary to route from the BGA pin pad
on top of the board to a via. The signal pair is routed from each via by striplines on Layer 5
as shown in
adjacent to all of the GTX transceiver signal pins. Having adjacent ground pins leads to
adjacent BGA breakout vias. The adjacent ground vias provide a return current path for the
signal via as the signal propagates from one layer to another layer in the stackup. If the two
layers that are connected to the signal via have separate ground planes, the adjacent
ground via provides a return current path in the Z-axis and thereby reduces the inductance
of the via.
X-Ref Target - Figure 5-15
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290
Stripline Routing from Via on Layer 3
GTX TX Pairs Routed on Microstrip to Via
• 50Ω Single-ended Microstrip for Each
Output
• 40 mil Separation on Vias Provides Z-axis
Return Current Path
• Suggest Transition to Layer 3 Which
Provides Return Current Path
Continuity
Figure 5-14: TX Microstrip Breakout
Figure 5-15. The Virtex-6 FPGA packages have been designed with grounds
GTX RX Pair Routed as Stripline
on Layer 5
Short 'Dog Bone' from BGA Pin
Pad to Via
BGA Pins
Figure 5-15: RX BGA Breakout to Stripline
www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Vias
UG366_c5_14_051509
RxP Via
RxN Via
Adjacent
GND Via
UG366_c5_15_051509