Xilinx Virtex-6 FPGA User Manual page 116

Chapter 2: Shared Transceiver Features
Table 2-9: PLL Attributes (Cont'd)
Attribute
TX_TDCC_CFG
TXPLL_COM_CFG
RXPLL_COM_CFG
TXPLL_CP_CFG
RXPLL_CP_CFG
TXPLL_DIVSEL_FB
RXPLL_DIVSEL_FB
TXPLL_DIVSEL_OUT
RXPLL_DIVSEL_OUT
TXPLL_DIVSEL_REF
RXPLL_DIVSEL_REF
TXPLL_DIVSEL45_FB
RXPLL_DIVSEL45_FB
TXPLL_LKDET_CFG
RXPLL_LKDET_CFG
TXPLL_SATA
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116
Type
2-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Binary Transceiver Wizard.
24-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Hex Transceiver Wizard.
8-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Hex Transceiver Wizard.
Integer This attribute is N2 in
feedback dividers. Common settings are 1, 2, 4, and 5.
Integer This attribute is D in
which resides in the clock divider block. Valid settings are 1, 2, and 4.
Integer This attribute is M in
divider. Common settings are 1 and 2.
Integer This attribute is N1 in
Valid settings are 4 and 5.
3-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Binary Transceiver Wizard.
2-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Binary Transceiver Wizard.
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Description
Figure 2-9. This attribute specifies one of the two PLL
Equation 2-2. It specifies the value of the PLL output divider,
Figure 2-9. It specifies the value for the reference clock input
Figure 2-9. It specifies one of the two PLL feedback dividers.
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011