Xilinx Virtex-6 FPGA User Manual page 313

Table B-1: Attributes DRP Address Map (Cont'd)
DADDR DRP Bits R/W
15:10
3Eh 9:5 R/W
4:0
15:8
R/W
3Fh
7:0
15:0 R/W
40h
31:16
41h
R/W
15:0
42h
15:6
5:3
R/W
43h
2:0
15:10
44h R/W
9:0
15:12
11:6 R/W
45h
5:0
15:10
R/W
46h
9:0
15:10
R/W
47h
9:0
15:0 R/W
48h
15:0 R/W
49h
15:0 R/W
4Ah
15
14
13:11 R/W
4Bh
10:6
5:3
2:0
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Attribute Name
Reserved
TX_DEEMPH_1
TX_DEEMPH_0
Reserved
TRANS_TIME_RATE
Reserved
TST_ATTR
TST_ATTR
Reserved
RXRECCLK_CTRL
TXOUTCLK_CTRL
Reserved
POWER_SAVE
Reserved
TX_USRCLK_CFG
TX_BYTECLK_CFG
Reserved
RXRECCLK_DLY
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RX_EN_REALIGN_RESET_BUF2
Reserved
RX_DLYALIGN_EDGESET
TX_DLYALIGN_MONSEL
RX_DLYALIGN_MONSEL
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Attribute Bits Attribute Encoding
5:0
4:0 0-31
4:0 0-31
7:0
7:0
15:0
31:16
15:0
9:0
RXRECCLKPCS
OFF_HIGH
OFF_LOW
2:0 RXPLLREFCLK_DIV1
RXPLLREFCLK_DIV2
RXRECCLKPMA_DIV1
RXRECCLKPMA_DIV2
TXOUTCLKPCS
OFF_HIGH
OFF_LOW
2:0 TXOUTCLKPMA_DIV1
TXOUTCLKPMA_DIV2
TXPLLREFCLK_DIV1
TXPLLREFCLK_DIV2
5:0
9:0 0-1023
3:0
5:0
5:0
5:0
9:0 0-1023
5:0
9:0
15:0
15:0
15:0
FALSE
TRUE
2:0
4:0 0-31
2:0 0-7
2:0 0-7
DRP Binary
Encoding
(1)
1
(1)
1
000
110
101
011
100
001
010
000
110
101
001
010
011
100
(1)
1
(1)
1
0
1
(1)
1
(1)
1
(1)
1
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