Xilinx Virtex-6 FPGA User Manual page 281

Figure 5-6
defined as MGTREFCLKP – MGTREFCLKN.
X-Ref Target - Figure 5-6
+ V MGTREFCLKP - MGTREFCLKN
0
– V
Figure 5-6: Differential Clock Input Voltage Swing, Peak-to-Peak
Figure 5-7
X-Ref Target - Figure 5-7
Figure 5-8
reference clock input pair MGTREFCLKP/MGTREFCLKN is internally terminated with
100 differential impedance. The common mode voltage of this differential reference clock
input pair is 4/5 of MGTAVCC, or nominal 0.8V. MGTAVCC is nominally 1.0V, hence the
common mode voltage is nominally 800 mV. The resistor values given in
nominal. Refer to the Virtex-6 FPGA Data Sheet for exact specifications.
X-Ref Target - Figure 5-8
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
illustrates the differential clock input voltage swing, peak-to-peak, which is
shows the rise and fall time convention of the reference clock.
80%
20%
T
FCLK
Figure 5-7: Rise and Fall Times
illustrates the internal details of the IBUFDS. The dedicated differential
MGTREFCLKP
MGTREFCLKN
Figure 5-8: MGTREFCLK Input Details
www.xilinx.com
T
RCLK
50Ω
4/5 MGTAVCC
50Ω
Reference Clock
V
IDIFF
UG366_c5_06_051509
UG366_c5_07_051509
Figure 5-8 are
to GTX
Dedicated
Clock
REFCLK
Routing
UG366_c5_08_051809
281