Table 1-1: Port and Attribute Summary (Cont'd)
RX Buffer Bypass
RX Elastic Buffer
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Port/Attribute
Ports:
•
RXCHARISCOMMA[3:0]
•
RXCHARISK[3:0]
•
RXDEC8B10BUSE
•
RXDISPERR[3:0]
•
RXNOTINTABLE[3:0]
•
RXRUNDISP[3:0]
Attributes:
•
DEC_MCOMMA_DETECT
•
DEC_PCOMMA_DETECT
•
DEC_VALID_COMMA_ONLY
•
RX_DATA_WIDTH
•
RX_DECODE_SEQ_MATCH
Ports:
•
RXDLYALIGNDISABLE
•
RXDLYALIGNMONENB
•
RXDLYALIGNMONITOR[7:0]
•
RXDLYALIGNOVERRIDE
•
RXDLYALIGNRESET
•
RXDLYALIGNSWPPRECURB
•
RXDLYALIGNUPDSW
•
RXENPMAPHASEALIGN
•
RXPLLLKDET
•
RXPLLLKDETEN
•
RXPMASETPHASE
•
RXRECCLK
•
RXUSRCLK
Attributes:
•
RX_BUFFER_USE
•
RX_DATA_WIDTH
•
RX_DLYALIGN_CTRINC
•
RX_DLYALIGN_EDGESET
•
RX_DLYALIGN_LPFINC
•
RX_DLYALIGN_MONSEL
•
RX_DLYALIGN_OVRDSETTING
•
RX_XCLK_SEL
•
RXRECCLK_CTRL
•
RXUSRCLK_DLY
•
PMA_RXSYNC_CFG
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Port and Attribute Summary
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