Chapter 1: Transceiver and Tool Overview
X-Ref Target - Figure 1-3
To FPGA Logic
From FPGA Logic
To FPGA Logic
From FPGA Logic
To FPGA Logic
From FPGA Logic
To FPGA Logic
From FPGA Logic
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22
From/To Adjacent Quad
TX-P2S
PCS
CLKs TX PLL
RX DFE, CDR, S2P
CLKs RX PLL
TX-P2S
PCS
CLKs TX PLL
RX DFE, CDR, S2P
CLKs RX PLL
TX-P2S
PCS
CLKs TX PLL
RX DFE, CDR, S2P
CLKs RX PLL
TX-P2S
PCS
CLKs TX PLL
RX DFE, CDR, S2P
CLKs RX PLL
From/To Adjacent Quad
Figure 1-3: Quad Configuration
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TX0
RX0
TX1
RX1
TX2
RX2
TX3
RX3
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
MGTREFCLK0
MGTREFCLK1
UG366_c1_03_051509