Xilinx Virtex-6 FPGA User Manual page 233

Table 4-40: RX Buffer Bypass Ports
Port
RXDLYALIGNDISABLE
RXDLYALIGNMONENB
RXDLYALIGNMONITOR[7:0] Out
RXDLYALIGNOVERRIDE
RXDLYALIGNRESET
RXDLYALIGNSWPPRECURB
RXDLYALIGNUPDSW
RXENPMAPHASEALIGN
RXPLLLKDET
RXPLLLKDETEN
RXPMASETPHASE
RXRECCLK
RXUSRCLK
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Dir Clock Domain
In Async RX delay aligner enable/disable signal. When driven Low, it
enables the delay phase aligner.
In Async RX delay aligner monitor enable/disable. When driven Low, this
port enables the RX delay aligner monitor.
Async Reserved.
In Async RX delay aligner override. This port must always be tied High.
The delay value is set manually from the
RX_DLYALIGN_OVRDSETTING[7:0] attribute.
In Async Resets the RX delay aligner.
In Async Reserved. It must be tied High.
In Async Reserved. It must be tied Low.
In Async When activated, the GTX receiver can align its XCLK with its
RXUSRCLK.
Out Async Indicates that the VCO rate is within acceptable tolerances of the
desired rate when High. The GTX transceiver does not operate
reliably until this condition is met.
In Async Enables the RX PLL lock detector. It must be tied High.
In Async When activated this pin aligns the PMA receiver recovered clock
with the PCS RXUSRCLK, allowing the RX elastic buffer to be
bypassed.
Out N/A This is the recommended clock output to the fabric. The attribute
RXRECCLK_CTRL is the input selector for RXRECCLK and
allows the RX PLL input reference clock or the recovered clocks
to be output to fabric.
In N/A Use this port to provide a clock for the internal RX PCS datapath.
The rate for RXUSRCLK depends on RX_DATA_WIDTH.
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RX Buffer Bypass
Description
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