Xilinx Virtex-6 FPGA User Manual page 119
Gtx transceivers
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Table 2-10: PLL Divider Settings for Common Protocols (Cont'd)
Line Rate
Standard
[Gb/s]
6.144
4.9152
3.072
CPRI 1-10X
(Multi-Rate)
2.4576
1.2288
0.6144
3.072
OBSAI
1.536
(Multi-Rate)
0.768
3G-SDI
2.97
HD-SDI
1.485
(Multi-Rate)
6.25
Interlaken
4.25
3.125
SFI-5
3.125
OC-48
2.48832
OC-12
0.62208
OTU-1
2.666057
Some protocols are shown twice as a single-rate configuration and a multi-rate
configuration. In single-rate configurations, only one line rate is required, and the
reference clock is optimized for that particular line rate. In multi-rate configurations, a
reference clock is selected for the highest line rate, and the appropriate dividers are
selected to support the lower line rates.
The general guidelines for the maximum, typical, and minimum frequencies for a given
protocol and line rate are:
•
•
•
•
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Internal Data
PLL Frequency
Width
[GHz]
[16b/20b]
20b
3.072
20b
2.4576
20b
3.072
20b
2.4576
20b
2.4576
1.2288
20b
20b
1.536
20b
1.536
20b
1.536
20b
1.485
20b
1.485
16b
3.125
16b
2.125
16b
3.125
16b
3.125
16b
2.48832
16b
1.24416
16b
2.666057
Maximum frequency is selected to use the minimum PLL multiplication ratio. This
option usually provides the highest jitter performance.
Typical reference clock frequency is selected to limit the PLL multiplication to either
8 or 10 depending on the protocol.
For lower line rate operation, the minimum frequency is selected to allow for a PLL
multiplication of 16 or 20.
Performance impact needs to be carefully considered if a reference clock below the
typical recommended frequency is used. Refer to the Virtex-6 FPGA Data Sheet for the
minimum and maximum reference clock frequencies.
www.xilinx.com
Using Typical REFCLK
REFCLK
Frequency
(Typical)
[MHz]
N1
N2
307.2
5
2
307.2
4
2
307.2
5
2
307.2
4
2
307.2
4
2
307.2
4
2
153.6
5
2
153.6
5
2
153.6
5
2
148.5
5
2
148.5
5
2
312.5
5
2
212.5
5
2
156.25
5
4
195.3125
4
4
155.52
4
4
155.52
4
2
166.6286
4
4
PLL
D
M
1
1
1
1
2
1
2
1
4
1
4
2
1
1
2
1
4
1
1
1
2
1
1
1
1
1
2
1
2
1
2
1
4
1
2
1
119
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