Xilinx Virtex-6 FPGA User Manual page 234

Chapter 4: Receiver
Table 4-41
Table 4-41: RX Buffer Bypass Attributes
Attribute
POWER_SAVE
RX_BUFFER_USE
RX_DATA_WIDTH
RX_DLYALIGN_CTRINC
RX_DLYALIGN_EDGESET
RX_DLYALIGN_LPFINC
RX_DLYALIGN_MONSEL
RX_DLYALIGN_OVRDSETTING
RX_XCLK_SEL
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234
defines the RX buffer bypass attributes.
Type
10-bit POWER_SAVE[4]:
Binary
Mux select for the TXOUTCLK output clock. Must be tied to 1'b1.
1'b0: Use the TX Delay Aligner
1'b1: Bypass the TX Delay Aligner
POWER_SAVE[5]:
Mux select for the RXRECCLK output clock. Must be tied to 1'b1 when
RX buffer is used (RX_BUFFER_USE = TRUE). When RX buffer is
bypassed, refer to
Buffer, page 235.
1'b0: Use the RX Delay Aligner
1'b1: Bypass the RX Delay Aligner
All other bits are reserved. Use recommended values from the Virtex-6
FPGA GTX Transceiver Wizard.
Boolean Use or bypass the RX elastic buffer.
TRUE: Use the RX elastic buffer (normal mode).
FALSE: Permanently bypass the RX elastic buffer (advanced feature).
Integer Sets the receiver external data width.
8/10: 1 byte interface
16/20: 2 byte interface
32/40: 4 byte interface
If 8B10B is used, this attribute must be a multiple of 10.
4-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Binary Transceiver Wizard.
5-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Binary Transceiver Wizard.
4-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Binary Transceiver Wizard.
3-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Binary Transceiver Wizard.
8-bit Sets the overdrive value for the RX delay aligner. This attribute takes
Binary effect when RXDLYALIGNOVERRIDE is driven High. This attribute
must be set to 8'b10000000.
String Selects the clock used to drive the RX parallel clock domain (XCLK).
"RXREC": (default) XCLK domain driven by recovered clock from
CDR. When OVERSAMPLE_MODE is TRUE, the recovered clock is
sourced from the oversampling block.
"RXUSR": RXUSRCLK port drives RX parallel clock domain. Use
this mode when bypassing the RX elastic buffer.
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Description
Using the RX Phase Alignment Circuit to Bypass the
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011