Xilinx Virtex-6 FPGA User Manual page 225

Table 4-35: RX Comma Alignment Attributes (Cont'd)
Attribute
RX_SLIDE_MODE
RX_SLIDE_AUTO_WAIT
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Type
String Defines the RXSLIDE mode:
OFF: This is the default setting. The RXSLIDE feature is not used.
PCS: The PCS is used to perform the bit slipping function. RXSLIDE is
driven High for one RXUSRCLK2 cycle to shift the parallel data
(RXDATA) to the left by one bit. In this mode, even if the RXRECCLK
is sourcing from the RX PMA, the clock phase remains the same.
PMA: The PMA is used to perform the bit slipping function. RXSLIDE
is driven High for one RXUSRCLK2 cycle to shift the parallel data
(RXDATA) to the right by one bit. If RXRECCLK is sourcing from the
RX PMA, its phase might be changed. This mode provides minimum
variation of latency compared to PCS mode. This option requires
SHOW_REALIGN_COMMA to be FALSE.
AUTO: This is an automated PMA mode without using the FPGA logic
to monitor the RXDATA and issue RXSLIDE pulses. In this mode,
RXSLIDE is ignored. In PCIe applications, this setting is used for FTS
lane deskew. This option requires SHOW_REALIGN_COMMA to be
FALSE.
Integer Defines how long the PCS waits for the PMA to auto slide (in terms of
RXUSRCLK clock cycles) before checking the alignment again. Valid
settings are from 0 to 15. The default value is 5. Only recommended
values from the Virtex-6 FPGA GTX Transceiver Wizard should be used.
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RX Byte and Word Alignment
Description
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