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Xilinx Virtex-5 RocketIO GTP User Manual

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Virtex-5 RocketIO GTP
Transceiver User Guide
UG196 (v1.3) May 25, 2007
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Summary of Contents for Xilinx Virtex-5 RocketIO GTP

  • Page 1 Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 2: Revision History

    Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.
  • Page 3 Appendix D: Added PCS_COM_CFG to Table D-2, Table D-7, and Table D-8. Revised bit 4 and 6 in Table D-3. Appendix E: Added note 2 to Table E-2, page 311. Added Appendix UG196 (v1.3) May 25, 2007 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide...
  • Page 4 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 5: Table Of Contents

    ..........52 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com...
  • Page 6 ....... 93 TXOUTCLK Driving a GTP TX in 1-Byte Mode www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 7 ..........120 SATA OOB Signaling Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com...
  • Page 8 ..........153 Alignment Status Signals www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 9 ............188 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com...
  • Page 10 ........216 Section 2: Board Level Design www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 11 ............252 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com...
  • Page 12 ..............315 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 13: Preface: About This Guide

    Appendix A, “MGT to GTP Transceiver Design Migration” ♦ Appendix B, “OOB/Beacon Signaling” ♦ Appendix C, “8B/10B Valid Characters” ♦ Appendix D, “DRP Address Map of the GTP_DUAL Tile” ♦ Appendix E, “Low Latency Design” Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 14: Additional Documentation

    • Virtex-5 Packaging Specifications This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 15: Additional Support Resources

    13. XAPP562, Configurable LocalLink CRC Reference Design Additional Support Resources To search the database of silicon and software questions and answers, or to create a technical support case in WebCase, see the Xilinx website at: http://www.xilinx.com/support. Typographical Conventions This document uses the following typographical conventions. An example illustrates each convention.

  • Page 16: Online Document

    Cross-reference link to a location Figure 5 in the Virtex-5 Data Red text in another document Sheet Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest documentation. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 17: Section 1: Fpga Level Design

    This section includes the following chapters: “Introduction to the RocketIO GTP Transceiver” “RocketIO GTP Transceiver Wizard” “Simulation” “Implementation” “Tile Features” “GTP Transmitter (TX)” “GTP Receiver (RX)” “Cyclic Redundancy Check (CRC)” “Loopback” “GTP-to-Board Interface” Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 18 Section 1: FPGA Level Design www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 19: Chapter 1: Introduction To The Rocketio Gtp Transceiver

    Out of band signaling, including COM signal support for PCI Express and SATA Table 1-1 lists some of the standard protocols designers can implement using the GTP transceiver. The Xilinx CORE Generator™ tool includes a Wizard to automatically configure GTP transceivers to support one of these protocols or perform custom configuration (see Chapter 2, “RocketIO GTP Transceiver...
  • Page 20 The Virtex-5 Ethernet MAC User Guide provides detailed information on the Ethernet MAC. • The Virtex-5 Integrated Endpoint Block User Guide for PCI Express Designs provides detailed information on PCI Express compliance. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 21 1. This figure does NOT illustrate exact size, location or scale of the functional blocks to each other. It does show the correct number of available resources. Figure 1-1: GTP_DUAL Inside the Virtex-5 LX110T FPGA Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 22 RX-PCS RXVALID1[1:0] UG196_c1_02_041307 Notes: 1. CLKIN is a simplification for a clock source. See Figure 5-3, page 69 for details on CLKIN. Figure 1-2: GTP_DUAL Tile Block Diagram www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 23: Ports And Attributes

    Analog Design pair for the reference clock of Guidelines (page 202) MGTREFCLKN the GTP_DUAL tile. Reference resistor input for Analog Design MGTRREF the entire device. Guidelines (page 202) Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 24 (DRP) (page 87) Starts the full GTP_DUAL reset GTPRESET Async Reset (page 73) sequence. Factory test pins. Must be strapped GTPTEST[3:0] Async Low for normal operation. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 25 (active Low). Reset (page 73), RESETDONE0 Indicates when the GTP transceiver has Async Clock Data Recovery finished reset and is ready for use. RESETDONE1 (CDR) (page 136) Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 26 Asserted when RXDATA is an 8B/10B Configurable 8B/10B RXUSRCLK2 K character. Decoder (page 157) RXCHARISK1[1:0] Configurable Channel RXCHBONDI0[2:0] FPGA channel bonding control. Used RXUSRCLK Bonding (Lane Deskew) only by slaves. RXCHBONDI1[2:0] (page 176) www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 27 Aligns the byte boundary when comma RXUSRCLK2 Alignment and plus is detected. RXENPCOMMAALIGN1 Detection (page 150) RXENPRBSTST0[1:0] PRBS Detection RXUSRCLK2 Receiver test pattern checker control. (page 147) RXENPRBSTST1[1:0] Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 28 8B/10B encoder when RXDATA is Decoder (page 157) RXRUNDISP1[1:0] received. Implements a comma alignment bump Configurable Comma RXSLIDE0 RXUSRCLK2 control, allowing manual comma Alignment and RXSLIDE1 alignment. Detection (page 150) www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 29 TXCOMTYPE Signaling (page 119) TXCOMSTART1 (SATA only). TXCOMTYPE0 Selects the type of COM signal to send TX OOB/Beacon TXUSRCLK2 (SATA only). Signaling (page 119) TXCOMTYPE1 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 30 GTP transceivers in the GTP_DUAL Alignment, and Buffer tile. Bypass (page 104) TXPOLARITY0 Specifies if the final transmitter output TX Polarity Control TXUSRCLK2 TXPOLARITY1 is inverted. (page 108) www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 31 (Lane Deskew) (page 177) CHAN_BOND_LEVEL_1 CHAN_BOND_MODE_0 Defines the channel bonding mode of Configurable Channel Bonding operation for the transceiver. (Lane Deskew) (page 177) CHAN_BOND_MODE_1 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 32 Configurable Clock Correction retain at least one clock correction sequence (page 170) CLK_COR_KEEP_IDLE_1 in the byte stream. CLK_COR_MAX_LAT_0 Specifies the maximum elastic buffer Configurable Clock Correction latency. (page 170) CLK_COR_MAX_LAT_1 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 33 CLKINDC_B dedicated reference clock inputs must be Clocking (page 70) AC coupled. COM_BURST_VAL_0[3:0] Number of bursts transmitted for a SATA TX OOB/Beacon Signaling COM sequence. (page 120) COM_BURST_VAL_1[3:0] Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 34 Configurable Comma PCOMMA_DETECT_0 Set to TRUE to allow plus comma detection Alignment and Detection and alignment. PCOMMA_DETECT_1 (page 152) PCS_COM_CFG Shared PLL configuration settings. Shared PMA PLL (page 61) www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 35 Sets RX termination voltage to VTTRX. Equalization (page 126) RCV_TERM_VTTRX_1 RX_BUFFER_USE_0 Configurable RX Elastic Buffer Set to TRUE to use the RX elastic buffer. and Phase Alignment (page 163) RX_BUFFER_USE_1 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 36 Used to set the minimum time allowed for a SATA_MIN_INIT_0 RX OOB/Beacon Signaling COMINIT/COMRESET Idle for the SATA (page 132) SATA_MIN_INIT_1 detector in terms of squelch clock cycles. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 37: Sim_Gtpreset_Speedup

    (page 113) TX_DIFF_BOOST_1 emphasis values. Overall differential swing is reduced when TX_DIFF_BOOST is TRUE. This parameter must be left at its default TX_SYNC_FILTERB value of 1. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 38 TXRX_INVERT0 paths within the GTP transceiver. When TX Buffering, Phase Alignment, bypassing the TX buffer, set to 00100. and Buffer Bypass (page 105) TXRX_INVERT1 Otherwise, set to 00000. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 39 The RocketIO GTP Transceiver Wizard is the preferred tool to generate a wrapper to instantiate a GTP_DUAL primitive. The Wizard can be found in the Xilinx CORE Generator tool. Be sure to download the most up-to-date IP Update before using the Wizard.
  • Page 40 Chapter 2: RocketIO GTP Transceiver Wizard www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 41: Overview

    1]) explains how to set up the simulation environment for supported simulators depending on the used Hardware Description Language (HDL). This design guide can be downloaded from the Xilinx website at http://www.xilinx.com/support/sw_manuals/xilinx9/download/ The prerequisites for simulating a design with GTP transceivers are: •...

  • Page 42: Ports And Attributes

    GTP_DUAL tile that can only be modeled in a limited way with an HDL simulator. The shared PMA PLL is another analog block in the GTP_DUAL that is www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 43: Smartmodel Attributes

    To simulate correctly, the Link Idle Reset circuit described in “Reset,” page 72 must be implemented and connected to each GTP_DUAL instance. This circuit is included automatically when the Wizard is used to configure the GTP_DUAL instance. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 44: Toggling Gsr

    Simulating in Verilog The GSR and global 3-state (GTS) signals are defined in the $XILINX/verilog/src/glbl.v module. The glbl.v module connects the global signals to the design, which is why it is necessary to compile this module with the other design files and load it along with the design.v and testfixture.v files for simulation.
  • Page 45 SRP <= '1', '0' after CLK_PERIOD * 25; Further details can be found in the Synthesis and Simulation Design Guide, which can be downloaded from the Xilinx website at http://www.xilinx.com/support/sw_manuals/xilinx9/download/ Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 46: Examples

    SIM_PLL_PERDIV2. 1. If there is a contradiction between this example and the documentation of your simulator, the simulator documentation has precedence. If a newer version of the Xilinx ISE development system is used, check the Xilinx website for additional information.
  • Page 47 To calculate PLL SPEED and SIM_PLL_PERDIV2 for the XAUI example, the following values are assigned: • REFCLK = 156.25 MHz • PLL_DIVSEL_REF = 1 • DIV = 5 • PLL_DIVSEL_FB = 2 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 48 Equation 3-2, PLL SPEED is 1.5625 GHz, meaning that the period is 640 ps. Using Equation 3-3, SIM_PLL_PERDIV2 is 640 divided by 2 or 320 decimal (140 hexadecimal). www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 49: Overview

    Differential receive data pairs for GTP RX Clock transceivers 0 and 1 MGTRXP1 MGTRXN1 MGTREFCLKP Differential reference clock input pair MGTREFCLKN MGTAVCCPLL Analog Analog Pad for 1.2V supply for PLL Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 50: Chapter 4: Implementation

    Care must be taken to ensure that all of the parameters needed to configure the GTP_DUAL tile are correctly entered. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 51: Example Of A Ucf For Gtp_Dual Placement

    (tile_num = 1; tile_num <= 7; ++tile_num) begin: gtp_dual GTP_DUAL gtp_dual .CLKIN(refclk), … The remaining GTP_DUAL ports are not shown endgenerate // Instantiate the IBUFDS for the reference clock IBUFDS ref_clk_buffer .IN(refclk_pad_n), .IP(refclk_pad_p), .O(refclk) Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 52: Package Placement Information

    Placement Name MGTAVCCPLL_116 MGTREFCLKP_116 MGTREFCLKN_116 MGTAVCC_116 MGTRXP1_116 MGTAVCC_116 MGTRXN1_116 MGTRXP0_116 MGTAVTTRX_116 GTP_DUAL_X0Y3 MGTRXN0_116 MGTTXP1_116 MGTAVTTTX_116 MGTAVTTTX_116 MGTTXN1_116 MGTTXP0_116 MGTTXN0_116 Board-Level Pin Numbers UG196_c4_01_102006 Figure 4-1: Placement Diagram Nomenclature www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 53 MGTRXN1_118 XC5VLX30T: GTP_DUAL_X0Y0 MGTRXP0_118 XC5VLX50T: GTP_DUAL_X0Y1 MGTAVTTRX_118 XC5VSX35T: GTP_DUAL_X0Y0 MGTRXN0_118 XC5VSX50T: GTP_DUAL_X0Y0 MGTTXP1_118 MGTAVTTTX_118 MGTAVTTTX_118 MGTTXN1_118 MGTTXP0_118 MGTTXN0_118 UG196_c4_02_012007 Figure 4-2: XC5VLX30T-FF665, XC5VLX50T-FF665, XC5VSX35T-FF665, and XC5VSX50T-FF665 GTP Placement Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 54 MGTAVTTRX_112 XC5VLX110T: GTP_DUAL_X0Y4 MGTRXN0_112 XC5VSX50T: GTP_DUAL_X0Y3 XC5VSX95T: GTP_DUAL_X0Y4 MGTTXP1_112 MGTAVTTTX_112 MGTTXN1_112 MGTAVTTTX_112 MGTTXP0_112 MGTTXN0_112 UG196_c4_03_012007 Figure 4-3: XC5VLX50T-FF1136, XC5VLX85T-FF1136, XC5VLX110T-FF1136, XC5VSX50T-FF1136, and XC5VSX95T-FF1136 GTP Placement (1 of 2) www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 55 XC5VSX50T: Not Available XC5VSX95T: GTP_DUAL_X0Y0 AN10 MGTTXP1_126 AM10 MGTAVTTTX_126 MGTTXN1_126 AM5 MGTAVTTTX_126 MGTTXP0_126 MGTTXN0_126 UG196_c4_04_012007 Figure 4-4: XC5VLX50T-FF1136, XC5VLX85T-FF1136, XC5VLX110T-FF1136, XC5VSX50T-FF1136, and XC5VSX95T-FF1136 GTP Placement (2 of 2) Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 56 MGTAVCC_120 XC5VLX110T: GTP_DUAL_X0Y6 MGTRXP0_120 MGTAVTTRX_120 XC5VLX220T: GTP_DUAL_X0Y6 MGTRXN0_120 XC5VLX330T: GTP_DUAL_X0Y8 MGTTXP1_120 MGTAVTTTX_120 MGTTXN1_120 MGTAVTTTX_120 MGTTXP0_120 MGTTXN0_120 UG196_c4_05_110906 Figure 4-5: XC5VLX110T-FF1738, XC5VLX220T-FF1738, and XC5VLX330T-FF1738 GTP Placement (1 of 3) www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 57 XC5VLX110T: GTP_DUAL_X0Y2 MGTRXP0_118 MGTAVTTRX_118 XC5VLX220T: GTP_DUAL_X0Y2 MGTRXN0_118 XC5VLX330T: GTP_DUAL_X0Y4 MGTTXP1_118 AH3 MGTAVTTTX_118 MGTTXN1_118 AN3 MGTAVTTTX_118 MGTTXP0_118 MGTTXN0_118 UG196_c4_06_110906 Figure 4-6: XC5VLX110T-FF1738, XC5VLX220T-FF1738, and XC5VLX330T-FF1738 GTP Placement (2 of 3) Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 58 BB15 MGTRXN0_134 XC5VLX330T: GTP_DUAL_X0Y0 BA18 MGTTXP1_134 AY13 MGTAVTTTX_134 BA17 MGTTXN1_134 AY18 MGTAVTTTX_134 BA13 MGTTXP0_134 BA14 MGTTXN0_134 UG196_c4_07_110906 Figure 4-7: XC5VLX110T-FF1738, XC5VLX220T-FF1738, and XC5VLX330T-FF1738 GTP Placement (3 of 3) www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 59: Chapter 5: Tile Features

    • Set the reference clock source • Implement the Link Idle Reset circuit These steps are performed automatically when the Wizard is used to configure the GTP_DUAL tile. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 60: Shared Pma Pll

    (dividers ending with _OUT) are set to determine the TX and RX line rates for each transceiver. Ports and Attributes Table 5-1 defines the shared PMA PLL ports. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 61 1. In ISE 9.2i and above, this attribute is included in the GTP_DUAL instance. Older ISE versions require setting this attribute with the a user-constraints file (UCF) when a non-default value is needed. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com...

  • Page 62: Description

    The smallest possible divider values must be selected The programmable dividers allow support for various standards. Figure 5-2 shows a conceptual view of the shared PLL from which the PLL clock is generated. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 63 1.25 3.125 312.5 156.25 1.5625 Serial RapidIO 1.25 1.25 1.25 SATA II SATA I SAS II SAS I PCI Express 1.25 Infiniband 1.25 HD-SDI 1.485 148.5 148.5 1.485 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 64: Examples

    For XAUI, both TX and RX use a line rate of 3.125 Gb/s. b. Determine the internal datapath width. Because XAUI is an 8B/10B-encoded standard, an internal datapath width of 10 bits is required. See “Configurable 8B/10B Encoder,” page 98 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 65: Configuring The Shared Pll For

    2.488/2 = 1.244 GHz. Because this RX rate of 1.244 GHz is within the operating range of the PLL, the external divider (PLL_RXDIVSEL_OUT) must be one. The PLL clock rate is thus 1.244 x 1 = 1.244 GHz. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 66: Configuring The Shared Pll For Gigabit Ethernet

    Equation 5-4. The result is a ratio of two. 1.25 GHz PLL_DIVSEL_FB PLL_Clock ----------------------------------- --------------------------------- - ---------------------------------------------------- - Equation 5-4 × × 125 MHz PLL_DIVSEL_REF CLKIN www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 67: Configuring Shared Pll For Pci Express

    Select the smallest divider values that result in the required PLL divider ratio. In this case, using PLL_DIVSEL_FB = 5 and PLL_DIVSEL_REF = 2 results in a ratio of 2.5. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 68: Clocking

    Instead, the global clock resources of the FPGA are connected to the shared PMA PLL. GREFCLK clocking is not recommended for most designs because of the increased jitter introduced by the FPGA clock nets. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 69 MGTREFCLKP BUFR Clock CLKIN Dedicated IBUFDS Muxing Clock MGTREFCLKN Routing UG196_c5_03_110206 Note: Refer to Chapter 10, “GTP-to-Board Interface” REFCLK Guidelines for IBUFDS details. Figure 5-3: GTP Transceiver Clocking Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 70: Ports And Attributes

    Refer to Chapter 10, “GTP-to-Board Interface,” REFCLK Guidelines for IBUFDS details. IBUFDS GTP_DUAL MGTREFCLKP CLKIN MGTREFCLKN UG196_c5_04_110306 Figure 5-4: Single GTP_DUAL Tile Clocked Externally www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 71: Clocking From A Neighbor Gtp_Dual Tile

    The same oscillator must be used when the GTP transceivers are combined to form a single channel using channel bonding (see “Configurable Channel Bonding (Lane Deskew),” page 175). Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 72: Clocking Using Grefclk

    This section also includes the instructions for implementing the Link Idle Reset circuit. This circuit must be implemented with all instances of the GTP_DUAL tile to allow the RX CDR circuit to operate correctly. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 73: Ports And Attributes

    RXUSRCLK2 Resets the PRBS error counter. Powers down the shared PMA PLL. Driving PLLPOWERDOWN PLLPOWERDOWN Async from Low to High triggers a GTPRESET. There are no attributes in this section. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 74: Description

    • GTP0 transmit section (PMA and PCS) • GTP0 receive section (PMA and PCS) • GTP1 transmit section (PMA and PCS) • GTP1 receive section (PMA and PCS) www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 75: Gtp Reset When The Gtpreset Port Is Asserted

    To restart the CDR after an electrical idle condition, RXELECIDLERESET and RXENELCIDLERESETB must be asserted. “RX Clock Data Recovery (CDR),” page 136 describes the RXELECIDLERESET, RXENELECIDLERESETB, and the CDR circuit in more detail. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 76 CDR is in reset. In this case RXELECIDLE(0/1) can be used as a selection signal of a BUFGMUX to multiplex between the RXRECCLK(0/1) and a different CDR independent clock source. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 77: Resetting The Gtp_Dual Tile

    ✓ ✓ RX LOS State Machine ✓ ✓ ✓ ✓ ✓ RX Polarity ✓ ✓ ✓ ✓ ✓ ✓ PRBS Checker ✓ ✓ ✓ ✓ ✓ 5x Over-sampler Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 78 RXBUFRESET PRBS error PRBS Error counter PRBSCNTRESET Over-sampler error Over-sampler RXRESET Notes: 1. The recommended reset has the smallest impact on the other compents of the GTP_DUAL tile. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 79: Examples

    RX CDR must be reset when the data source is plugged in to ensure that it can lock to incoming data. Use RXELECIDLERESET to perform this reset. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 80 To clear the RXPRBSERR signal after the PRBS error threshold is exceeded, assert PRBSERRRESET. Oversampler Error If RXOVERSAMPLEERR goes High to indicate an overflow or underflow in the Oversampling block, assert RXRESET to clear it. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 81: Power Control

    10: P1 (longer recovery time; RecDet is still on) 11: P2 (lowest power state) Notes: 1. Because of the shared PMA PLL, a powerdown via PLLPOWERDOWN or REFCLKPWRDNB affects both channels. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 82: Description

    The GTP_DUAL tile provides several power control features that can be used in a wide variety of applications. Table 5-11 summarizes these capabilities. The Recovery Time column describes how long after a power control mode is disabled that normal operation can resume. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 83 TXPOWERDOWN[1] and TXPOWERDOWN[0] are connected together. • RXPOWERDOWN[1] and RXPOWERDOWN[0] are connected together. • TXDETECTRX must be strapped Low. • TXELECIDLE must be strapped to TXPOWERDOWN[1] and TXPOWERDOWN[0]. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 84: Power Control Features For Pci Express

    11 (P2 state) Don’t Care The PHY is idle. The GTP transceiver acknowledges changes in the PCI Express power mode by asserting the PHYSTATUS signal for one clock cycle. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 85: Powerdown Transition Times

    Disabled Transceiver TXPOWERDOWN0[1] TXPOWERDOWN0[1] TXPOWERDOWN0[0] TXPOWERDOWN0[0] PLLPOWERDOWN PLLPOWERDOWN REFCLKPWRDNB REFCLKPWRDNB Controlled TXPOWERDOWN1[1] TXPOWERDOWN1[1] Application TXPOWERDOWN1[0] TXPOWERDOWN1[0] RXPOWERDOWN1[1] RXPOWERDOWN1[1] RXPOWERDOWN1[0] RXPOWERDOWN1[0] UG196_c5_10_082906 Figure 5-10: Powering Down an Unused Tile Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 86 TXPOWERDOWN0[0] PLLPOWERDOWN REFCLKPWRDNB TXPOWERDOWN1[1] TXPOWERDOWN1[0] RXPOWERDOWN1[1] RXPOWERDOWN1[0] POWERDOWN[1] POWERDOWN[0] GTP_DUAL Tile RXPOWERDOWN0[1] RXPOWERDOWN0[0] TXPOWERDOWN0[1] TXPOWERDOWN0[0] PLLPOWERDOWN REFCLKPWRDNB TXPOWERDOWN1[1] TXPOWERDOWN1[0] RXPOWERDOWN1[1] RXPOWERDOWN1[0] UG196_c5_11_082906 Figure 5-11: 4x PIPE Compatible Configuration www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 87: Dynamic Reconfiguration Port (Drp)

    GTP_DUAL DRP attributes sorted alphabetically by name and by address. Stopping the reference clock during a DRP operation can prevent the correct termination of the operation. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 88 Chapter 5: Tile Features www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 89: Transmitter Overview

    “TX PRBS Generator,” page 109 “Parallel In to Serial Out (PISO),” page 110 “Configurable TX Driver,” page 112 “PCI Express Receive Detect Support,” page 116 “TX OOB/Beacon Signaling,” page 119 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 90: Fpga Tx Interface

    TXENC8B10BUSE is set High to enable the 8B/10B encoder. INTDATAWIDTH must also be High. TXENC8B10BUSE TXUSRCLK2 0: 8B/10B encoder bypassed. This option reduces latency. 1: 8B/10B encoder enabled. INTDATAWIDTH must be 1. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 91: Description

    “Configurable 8B/10B Encoder,” page Table 6-2: TX Datapath Width Configuration INTDATAWIDTH TXDATAWIDTH TXENC8B10BUSE FPGA TX Interface Width 8 bits 16 bits 10 bits 8 bits Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 92: Connecting Txusrclk And Txusrclk2

    TXUSRCLK2 is the main synchronization clock for all signals into the TX side of the GTP transceiver. Most signals into the TX side of the GTP transceiver are sampled on the www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 93: Examples

    TX interface. TXOUTCLK Driving a GTP TX in 1-Byte Mode Figure 6-4, TXOUTCLK is used to drive TXUSRCLK and TXUSRCLK2 for 1-byte mode (TXDATAWIDTH = 0). Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 94: Txoutclk Driving Gtp Tx In 2-Byte Mode

    CLKFB CLK0 PLLLKDET CLKDV TXOUTCLK CLKIN LOCKED BUFG Design In TXUSRCLK2 FPGA Transceiver TXUSRCLK TXDATA (16 or 20 bits) UG196_c6_05_051507 Figure 6-5: DCM Provides Clocks for 2-Byte Datapath www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 95: Txoutclk Driving Multiple Transceivers For A 2-Byte Datapath

    GTP transceivers, and they must share the same reference clock. In Figure 6-7, because the top GTP transceiver uses a two-byte interface, it requires a divided clock for TXUSRCLK2. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 96: Refclkout Driving Multiple Transceivers With A 2-Byte Interface

    REFCLKOUT. A DCM can be used instead of the PLL, but the PLL is more convenient when the REFCLKOUT rate is not an integer multiple of the required TXUSRCLK rates. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 97 CLKOUT1 REFCLKOUT Tile CLKIN Design in FPGA BUFG LOCKED TXUSRCLK2 Transceiver TXUSRCLK TXDATA (16 or 20 bits) UG196_c6_08_040907 Figure 6-8: REFCLKOUT Driving Multiple Transceivers with a 2-Byte Interface Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 98: Configurable 8B/10B Encoder

    The GTP transceiver includes an 8B/10B encoder to encode TX data without consuming FPGA resources. If encoding is not needed, the block can be disabled to minimize latency. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 99: Ports And Attributes

    K-character table of the 8B/10B table in TXCHARISK0[1:0] Appendix C, “8B/10B Valid Characters.” TXUSRCLK2 TXCHARISK1{1:0] TXCHARISK[1] corresponds to TXDATA[15:8], and TXCHARISK[0] corresponds to TXDATA[7:0]. TXCHARISK is undefined for bytes th at bypass 8B/10B encoding. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 100: Description

    (byte 0) must be placed on TXDATA[7:0], and the second placed on TXDATA[15:8]. This placement ensures that the byte 0 bits are all sent before the byte 1 bits, as required by 8B/10B encoding. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 101: K Characters

    Outgoing Disparity Calculated normally by the 8B/10B encoder Inverts normal running disparity when encoding TXDATA Forces running disparity negative when encoding TXDATA Forces running disparity positive when encoding TXDATA Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 102: 8B/10B Bypass

    The GTP transmitter includes a TX buffer and a TX phase-alignment circuit to resolve phase differences between the PMACLK and TXUSRCLK domains. All TX datapaths must use one of these circuits. Table 6-6 shows trade-offs between buffering and phase alignment. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 103 When oversampling is enabled (OVERSAMPLE_MODE = TRUE), the TX buffer is used for bit interpolation and must always be active. See “Oversampling,” page 143 for more information about built-in 5x oversampling. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 104: Ports And Attributes

    This clock must always be provided. Its rate depends on INTDATAWIDTH: TXUSRCLK0 • INTDATAWIDTH = 0: TXUSRCLK1 FTXUSRCLK = Line Rate/8 • INTDATAWIDTH = 1: FTXUSRCLK = Line Rate/10 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 105 Controls inverters that optimize the clock paths within the GTP transceiver for different modes of operation. The attribute must be set as follows: TXRX_INVERT0 00000: Use when TX_BUFFER_USE = TRUE TXRX_INVERT1 00100: Use when TX_BUFFER_USE = FALSE Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 106: Description

    GTP transceivers on the tile. TXOUTCLK cannot be the source for TXUSRCLK when the TX phase-alignment circuit is used. See “FPGA TX Interface,” page 90 for details. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 107: Using The Tx Phase Alignment Circuit To Minimize Tx Skew

    TXUSRCLK Transceiver BUFG or BUFR REFCLKOUT Dividers (if necessary) TXUSRCLK Transceiver UG196_c6_13_030507 Figure 6-13: TX Low-Skew Phase-Alignment Configuration Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 108: Tx Polarity Control

    The GTP transceiver can invert the polarity of its TX data before it is transmitted. This feature can be used to avoid hardware fixes for swapped TXP/TXN differential traces on a board. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 109: Tx Prbs Generator

    Specifies the width of the internal datapath for the entire GTP_DUAL. The INTDATAWIDTH Async PRBS Generator will only work when INTDATAWIDTH = 1 (10-bit internal datapath) There are no attributes in this section. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 110: Description

    GTP_DUAL tile. This shared port is also described INTDATAWIDTH Async “Shared PMA PLL,” page 0: Internal datapath is 8 bits wide 1: Internal datapath is 10 bits wide www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 111: Description

    × PLL Clock Rate 2 Equation 6-4 Tx Line Rate ------------------------------------------------------------------------------------------------------------------------------------------------------------ - × × PLL_TXDIVSEL_OUT PLL_TXDIVSEL_COMM_OUT “Oversampling,” page 143 for more information about oversampling. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 112: Configurable Tx Driver

    MGTAVTTTX TXPREEMPHASIS[2:0] MGTTXN Main Pre-Driver Pad Driver MGTTXP TxData[9:0] PISO TXDIFFCTRL[2:0] TXBUFDIFFCTRL[2:0] 10:1 Pre-emphasis Pre-Driver Pad Driver TX Serial Clock TXPREEMPHASIS[2:0] UG196_c6_14_051107 Figure 6-14: TX Driver Segments www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 113: Ports And Attributes

    Table 6-18 shows the expected transmitter pre-emphasis a percentage of overall TX swing. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 114: Pre-Emphasis

    Serial traces tend to attenuate high frequencies more than low frequencies. Pre-emphasis is a technique used to equalize transmitted data. It compensates for the excess high- frequency loss by transmitting high-frequency signals with more power than low- frequency signals. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 115: Configurable Termination Impedance

    The TX driver includes the TXINHIBIT port. When TXINHIBIT is driven High, the TX driver stops sending data and transmits only a differential 0 value (TXP High, TXN Low). Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 116: Pci Express Receive Detect Support

    110: Elastic Buffer Underflow. Different than defined in the PIPE specification. 111: Receive Disparity Error When RX_STATUS_FMT = SATA: RXSTATUS[0]: TXCOMSTART operation complete RXSTATUS[1]: COMWAKE signal received RXSTATUS[2]: COMRESET/COMINIT signal received www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 117: Description

    TERMT : 40-60Ω : 75-200 nF TERMR : < 3 nF TERMR TXDETECTRX GTP Transceiver Channel Far-End Receiver Components Components Components UG196_c6_15_080806 Figure 6-15: Receive Detection Circuit Model Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 118 (as signaled by the assertion of PHYSTATUS), TXDETECTRX must be deasserted. Figure 6-17 shows this process. TXUSRCLK2 TXDETECTRX RXPOWERDOWN[1:0] TXPOWERDOWN[1:0] PHYSTATUS RXUSRCLK2 RXSTATUS[2:0] 000b Status UG196_c6_17_080806 Figure 6-17: Receiver Detect Waveforms www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 119: Tx Oob/Beacon Signaling

    TX pair. TXELECIDLE1 TXPOWERDOWN0[1:0] Powers down TX lanes. The GTP_DUAL tile must be in the P2 power Async state (TXPOWERDOWN = 11) to generate beacon signaling. TXPOWERDOWN1[1:0] Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 120: Description

    The number of bursts in the COM sequence is controlled by the COM_BURST_VAL attribute. The timing of the COM sequences transmitted is correct as long as the PLL clock www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 121 When a TXCOMSTART operation completes, RXSTATUS[0] is driven High for one RXUSRCLK2 cycle. Be careful not to use the output of RXSTATUS[0] without synchronizing it to the TXUSRCLK2 domain if TXUSRCLK2 and RXUSRCLK2 are driven by separate clocks. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 122 Chapter 6: GTP Transmitter (TX) www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 123: Receiver Overview

    “Serial In to Parallel Out (SIPO),” page 141 “Oversampling,” page 143 “RX Polarity Control,” page 146 “PRBS Detection,” page 147 “Configurable Comma Alignment and Detection,” page 148 “Configurable Loss-of-Sync State Machine,” page 155 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 124 “Configurable 8B/10B Decoder,” page 157 “Configurable RX Elastic Buffer and Phase Alignment,” page 161 “Configurable Clock Correction,” page 168 “Configurable Channel Bonding (Lane Deskew),” page 175 “FPGA RX Interface,” page 182 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 125: Rx Termination And Equalization

    0xxx: Filter pole depends on resistor calibration 1000: 0% nominal pole 1001: -12.5% RXEQPOLE0[3:0] Async 1010: -25.0% RXEQPOLE1[3:0] 1011: -37.5% 1100: +12.5% 1101: +25.0% 1110: +37.5% 1111: +50.0% Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 126: Description

    The GTP_DUAL receivers are connected via differential pad pairs RXN and RXP to the transmission line on the board. Figure 7-2 illustrates the internal architecture of one receiver channel inside the GTP_DUAL block. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 127: Optional Built-In Ac Coupling

    To turn on built-in AC coupling, AC_CAP_DIS is set to FALSE, and RCV_TERM_MID is set to TRUE. To disable the built-in AC coupling, AC_CAP_DIS is set to TRUE, and RCV_TERM_MID is set to FALSE. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 128: Configurable Termination Impedance

    “PCI Express Receive Detect Support,” AC coupling page 108. Table 7-4: RX Termination Attribute Settings RX Termination Voltage RCV_TERM_GND RCV_TERM_VTTRX MGTAVTTRX FALSE TRUE 2/3 MGTAVTTRX FALSE FALSE TRUE FALSE www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 129: Optional Configurable Rx Linear Equalization

    The GTP_DUAL supports PCI Express based beacons by using interface signals defined in the PHY interface for the PCI Express (PIPE) specification. The FPGA logic decodes the beacon sequence. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 130: Ports And Attributes

    RXSTATUS[2]: COMRESET/COMINIT signal received Indicates symbol lock and valid data on RXDATA and RXCHARISK[1:0] RXVALID0 RXUSRCLK2 when High, as defined in the PHY Interface for PCI Express (PIPE) RXVALID1 specification. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 131 1 and 61 (the default is 22) and must be greater than SATA_MIN_INIT. SATA_MAX_INIT_1 See the “Description” section to learn how to calculate the best value for a given squelch clock rate. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 132: Description

    OOBDETECT_THRESHOLD attribute. This signal can be used to decode PCI Express beacon sequences. The latency between the arrival of an OOB signal and the assertion of RXELECIDLE is found in the Virtex-5 Data Sheet. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 133: Sata Oob Detection

    After calculating these in terms of squelch clock, the appropriate MAX parameter is set to an integer value between these two numbers. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 134: Example

    Shortest idle width that must be rejected for 2.357142857 COMWAKE MinWakeWidth Shortest idle width that must be accepted for 101.3 4.341428571 COMWAKE Nominal idle width for COMWAKE 106.7 4.572857143 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 135 Table 7-8: Example SATA Attribute Settings (Continued) Parameter cycles cycles cycles cycles cycles cycles Longest idle width that must be accepted for COMWAKE MaxWakeWidth Longest idle width that must be rejected for 13.1 COMWAKE Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 136: Rx Clock Data Recovery (Cdr)

    The “RX Clock Data Recovery (CDR)” section shows how this port must be connected for all GTP designs. 0: CDR reset function enabled 1: CDR reset function disabled www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 137: Description

    The RX CDR circuit can tolerate runs longer than 150 bits, but designers should take steps to limit the length of runs without transitions to 150 bits or fewer. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 138: Cdr Reset

    Internal RXBUFRESET High for 1 μs Total Reset time ~ 5 μs Deasserts 1 μs later Deasserts 1 μs later UG196_c7_05_080806 Figure 7-5: Reset Sequence Triggered by RXCDRRESET www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 139: Tuning The Cdr

    PMA_RX_CFG to put the CDR into lock-to-reference mode. Table 7-11: Required PMA_RX_CFG Setting for Different Operation Modes Application PMA_RX_CFG Setting Order Loop Normal operation mode 25’h09F0089 Oversampling mode 25’h09F0088 Lock-to-reference mode 25’h09F0000 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 140: Horizontal Sample Point Shift

    64, the nominal 90º sampling point. There are three fields to accommodate the different possible PLL_RXDIVSEL_OUT settings. Table 7-12 shows how to set PMA_CDR_SCAN for PLL_RXDIVSEL_OUT = 1. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 141: Serial In To Parallel Out (Sipo)

    This divider defines the nominal line rate for the receiver. It can be PLL_RXDIVSEL_OUT_0 set to 1, 2, or 4. PLL_RXDIVSEL_OUT_1 RX Line Rate = PLL Clock * 2/PLL_RXDIVSEL_OUT Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 142: Description

    Both the serial and parallel clocks for the SIPO are generated from the recovered clock in the CDR circuit. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 143: Oversampling

    Low. When High, indicates the FIFO in RXOVERSAMPLEERR0 oversampling circuit has either RXUSRCLK2 overflowed or underflowed. PCS must be RXOVERSAMPLEERR1 reset to resume proper operation. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 144: Description

    Oversampling mode automatically uses a 10-bit internal datapath in the PMA, regardless of the INTDATAWIDTH setting. The lowest possible ratio of PLL_CLKDIV_FB to PLL_CLKDIV_REF is recommended. × PLL_CLKDIV_FB × ---------------------------------------------------------- - Equation 7-6 PLLClock CLKIN PLL_CLKDIV_REF www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 145: Configuring The Pcs Internal Datapath And Clocks

    This error can be cleared by asserting RXRESET or RXCDRRESET. RXENSAMPLEALIGN is tied High so the oversampling block always attempts to find the best possible recovered clock and sample point in the incoming data. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 146: Rx Polarity Control

    The RX Polarity port is used to invert the polarity of incoming data. Driving this port High causes the RXN pin to be treated as RXP and the RXP pin to be treated as RXN. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 147: Prbs Detection

    If the number PRBS_ERR_THRESHOLD0 of errors exceeds the value of PRBS_ERR_THRESHOLD, the PRBS_ERR_THRESHOLD1 output RXPRBSERR goes High. This attribute is set as a 32-bit hex value. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 148: Description

    100101100001001001101011100110011100101111100 1011011001010100100010101 010101100110 Transmitted First All Subsequent Data Alignment Block Aligned to Correct Finds Comma Byte Boundary UG196_c7_10_092606 Figure 7-10: Conceptual View of Comma Alignment (Aligning to a 10-Bit Comma) www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 149: Ports And Attributes

    RXUSRCLK2 RXBYTEREALIGN1 1: Byte alignment has changed Data can be lost when alignment occurs, which can cause data errors (and disparity errors when the 8B/10B decoder is used). Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 150 RXSLIDE1 RXSLIDE must be deasserted for two RXUSRCLK2 cycles before it can be reasserted to cause another adjustment. When asserted, RXSLIDE takes precedence over normal comma alignment. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 151 Define comma plus to raise RXCOMMADET and align the parallel data. PCOMMA_10B_VALUE_0 Reception order is right to left. (PCOMMA_10B_VALUE[0] is received first.) The PCOMMA_10B_VALUE_1 default value is 0101111100 (K28.5). This definition does not affect 8B/10B encoding or decoding. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 152: Description

    INTDATAWIDTH (see “Shared PMA PLL,” page 60). Figure 7-13 shows how the commas are combined when COMMA_DOUBLE is TRUE. MCOMMA_10B_VALUE PCOMMA_10B_VALUE UG196_c7_13_092606 Figure 7-13: Extended Comma Pattern Definition www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 153: Activating Comma Alignment

    INTDATAWIDTH, and the number of legal boundary positions is determined by the number of bytes in the RXDATA interface. Figure 7-15 shows the boundaries that can be selected. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 154: Manual Alignment

    1. Latency between the slide and the slide result at RXDATA depends on the number of active RX PCS blocks in the datapath. Figure 7-16: Manual Data Alignment Using RXSLIDE www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 155: Configurable Loss-Of-Sync State Machine

    TRUE (default): Loss of sync FSM is in operation and its state is reflected on RXLOSSOFSYNC[1]. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 156: Description

    The LOS allows the error count in the SYNC_ACQUIRED state to decrease over time, so that sparse errors are eventually discarded. The rate that the error count is decreased is controlled by the RX_LOS_INVALID_INCR attributes, as defined in Table 7-23. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 157: Configurable 8B/10B Decoder

    RXRUNDISP is a two-bit signal. Bit 0 corresponds to the lower byte RXRUNDISP1[1:0] of RXDATA, and bit 1 corresponds to the upper byte. When RXDATAWIDTH = 0 (one-byte interface), only bit 0 is used. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 158: Description

    (byte 0) is presented on RXDATA[7:0], and the second byte is presented on RXDATA[15:8]. Figure 7-18 shows how the decoder maps 10-bit data to 8-bit values. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 159: K Characters And 8B/10B Commas

    8B/10B decoder detects illegal 10-bit codes (out-of-table errors). The decoder drives the RXNOTINTABLE port High when RXDATA is not a valid 8B/10B character. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 160 RXNOTINTABLE and RXDISPERR ports indicating the error. RXUSRCLK2 Good Disp Out of Both Good RXDATA Data Error Table Errors Data RXDISPERR RXNOTINTABLE UG196_c7_19_092606 Figure 7-19: RX Data with 8B/10B Errors www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 161: Configurable Rx Elastic Buffer And Phase Alignment

    Clock Correction/ Required for clock correction/channel Channel Bonding bonding Internal Data Width Can be 8 or 10 bits wide Must be 10 bits wide Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 162: Ports And Attributes

    1. If an RX buffer overflow or an RX buffer underflow condition occurs, the content of the RX buffer becomes invalid, and the RX buffer needs re-initialization by asserting RXBUFRESET. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 163: Description

    PCS Parallel clock domain (RXUSRCLK) in the RX datapath. This bridging is necessary because there is no guaranteed phase relationship between the parallel clock from the SIPO (XCLK) and the parallel clocks from the FPGA logic (RXUSRCLK and RXUSRCLK2). Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 164: Using Rx Phase Alignment

    SIPO (XCLK) and the parallel clocks from the FPGA logic (RXUSRCLK and RXUSRCLK2). Phase alignment causes RXRECCLK from the SIPO to be adjusted so that there is no significant phase difference between XCLK and RXUSRCLK. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 165 When the RX buffer is bypassed, data received from the PMA might be distorted due to phase differences as it passes to the PCS. This makes it difficult to determine whether bad Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 166 LOS State Machine Pass Final RXPMASETPHASE Assertion for Phase Alignment with Known CDR Lock (32 Cycles) Phase Alignment Done UG196_c7_34_102306 Figure 7-23: Steps Required for Successful RX Phase Alignment www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 167: Bypassing The Rx Buffer While Using Built-In Oversampling

    Set RX_XCLK_SEL to “RXUSR”. Source RXUSRCLK and RXUSRCLK2 with the RXRECCLK output. Divide RXRECCLK by 2 if necessary to provide RXUSRCLK2 (see “FPGA RX Interface,” page for details). Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 168: Configurable Clock Correction

    RXUSRCLK. The “Configurable RX Elastic Buffer and Phase Alignment” section has more details about the steps required if clock correction is not used. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 169: Ports And Attributes

    CLK_COR_ADJ_LEN_1 than in the specified clock correction sequence. Valid lengths are from one to four bytes. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 170 If this attribute is zero, no limit is placed on how frequently clock correction can occur. CLK_COR_REPEAT_WAIT_1 Valid values for this attribute range from 0 to 31. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 171 If this attribute is zero, no limit is placed on how frequently clock correction can occur. CLK_COR_REPEAT_WAIT_1 Valid values for this attribute range from 0 to 31. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 172: Description

    RX elastic buffer. To use clock correction, set RX_BUFFER to TRUE to turn on the elastic buffer, and set CLK_CORRECT_USE to TRUE to turn on the clock correction circuit. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 173: Setting Rx Buffer Limits

    When RX_DECODE_SEQ_MATCH is FALSE, the sequence must exactly match non- decoded incoming data. The bit order of the data matches the bit order shown in Figure 7-34 Figure 7-35 for RXDATA with no 8B/10B decoding. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 174: Clock Correction Options

    RX elastic buffer. To use the RXRUNDISP port to indicate inserted idles instead of the current RX running disparity, set CLK_COR_INSERT_IDLE_FLAG to TRUE. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 175: Configurable Channel Bonding (Lane Deskew)

    RX Data is Two Clock Cycles (Set to Two Cycles of Latency by Deskewed Data Behind GTP0 Data Channel Bonding Controller) GTP1 (Slave) UG196_c7_25_092606 Figure 7-28: Channel Bonding Conceptual View Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 176: Ports And Attributes

    It must always be less than the minimum distance (in bytes or 10-bit codes) between channel bonding CHAN_BOND_2_MAX_SKEW_0 sequences. CHAN_BOND_2_MAX_SKEW_1 Valid values range from 1 to 14. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 177 Determines if the second channel bonding sequence is to be used. CHAN_BOND_SEQ_2_USE_0 TRUE: Channel bonding can be triggered by channel bonding sequence 1 or CHAN_BOND_SEQ_2_USE_1 FALSE: Channel bonding is only triggered by sequence 1. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 178: Description

    Daisy chaining is performed using the CHAN_BOND_LEVEL signal to allow additional pipeline stages between the master and the slave. The RXCHBONDO port of each slave is used as a pipeline stage in the www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 179 1. Each box can represent either transceiver in a GTP_DUAL tile. 2. This structure can be implemented using from two to four GTP_DUAL tiles. Figure 7-30: Channel Bonding Daisy Chaining Example 2 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 180: Setting The Channel Bonding Sequence

    Figure 7-32 shows the mapping of the enable attributes for the channel bonding subsequences. CHAN_BOND_SEQ_x_4 CHAN_BOND_SEQ_x_3 CHAN_BOND_SEQ_x_2 CHAN_BOND_SEQ_x_1 CHAN_BOND_SEQ_x_ENABLE UG196_c7_29_092606 Figure 7-32: Channel Bonding Sequence Mapping www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 181: Setting The Maximum Skew

    To make clock correction a higher priority than channel bonding, CLK_COR_PRECEDENCE must be set to TRUE. To make channel bonding a higher priority, CLK_COR_PRECEDENCE must be set to FALSE. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 182: Fpga Rx Interface

    GTP transceiver is either a static 1 or a static 0. PCS RX system reset. Resets receiver elastic buffer, 8B/10B decoder, RXRESET Async comma detect, and other receiver registers. This is a per channel subset of GTPRESET. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 183: Description

    2. The internal datapath is 8 bits when INTDATAWIDTH = 0 and 10 bits when INTDATAWIDTH = 1. 3. The RXDATA interface is one byte wide when RXDATAWIDTH = 0 and two bytes wide when RXDATAWIDTH = 1. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 184: Connecting Rxusrclk And Rxusrclk2

    Most signals into the RX side of the GTP receiver are sampled on the positive edge of RXUSRCLK2. RXUSRCLK2 is the same rate at RXUSRCLK when RXDATAWIDTH www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 185 RXUSRCLK and RXUSRCLK2 must be driven by RXRECCLK, and the phase-alignment circuit must be used. If clock correction is used, RXUSRCLK and RXUSRCLK2 can be sourced by RXRECCLK, REFCLKOUT, or TXOUTCLK. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 186 Chapter 7: GTP Receiver (RX) www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 187: Chapter 8: Cyclic Redundancy Check (Crc)

    For a given GTP_DUAL, four independent 32-bit wide CRC modules are only possible when a 64-bit wide CRC module is not used. Figure 8-2 shows how CRC modules are typically used in an application. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 188: Ports And Attributes

    CRC value. Note: CRCDATAVALIDA must be driven High. Synchronous reset of CRC registers. When CRCRESET is asserted, CRCRESET CRCCLK the CRC block is initialized to the CRC_INIT value. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 189: Description

    CRC for the contents to confirm that no changes occurred. CRCs are simple to implement in digital hardware, easy to analyze mathematically, and good at detecting common errors caused by noise in transmission channels. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 190: The Crc Primitive

    Table 8-5: CRC64 – Valid Data Widths CRCDATAWIDTH[2:0] Data Width CRC Data Bus Bits 8-bit CRCIN[63:56] 16-bit CRCIN[63:48] 24-bit CRCIN[63:40] 32-bit CRCIN[63:32] 40-bit CRCIN[63:24] 48-bit CRCIN[63:16] 56-bit CRCIN[63:8] 64-bit CRCIN[63:0] www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 191: Using The Crc Blocks

    CRC_INIT values for some common protocols that use the CRC32 polynomial. Table 8-6: CRC_INIT Values for Some Common Protocols Protocol CRC_INIT Ethernet 32’hFFFF_FFFF PCI Express 32’hFFFF_FFFF Infiniband 32’hFFFF_FFFF Fibre Channel 32’hFFFF_FFFF SATA 32’h5232_5032 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 192 The CRC result for a given frame is the CRCOUT value corresponding to the final byte(s) of the frame. This value appears one cycle after the final byte(s) of the frame are presented to the CRCIN port with CRCDATAVALID High. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 193: Integrating The Crc Blocks For Tx

    CRC check passes. The residue value for CRC32, after bit inversion and byte reversal, is 32’h1CDF4421. • Remove the transmitted CRC from the frame, if necessary. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 194: Implementation Of The Crc Block

    The CRCOUT is Byte Rotated and Bit Inverted. CRCCLK UG196_c8_05_100506 Figure 8-5: CRC Implementation References Refer to XAPP209 [Ref 12] and XAPP562 [Ref 13] for more information on CRC. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 195: Chapter 9: Loopback

    9-1) • Near-End PMA Loopback (path 2 in Figure 9-1) • Far-End PMA Loopback (path 3 in Figure 9-1) • Far-End PCS Loopback (path 4 in Figure 9-1) Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 196: Ports And Attributes

    The test data is looped back before passing the parallel-to-serial and the serial-to- parallel converter. All analog high-speed circuits in the PMA section can be completely powered down. Figure 9-2 illustrates this configuration. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 197: Near-End Pma Loopback

    The inputs can be left unconnected. When the device is on a board, the remote transmitter should be 3-stated. If this is not possible, then the following alternatives are available: Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 198: Far-End Pma Loopback

    When one channel of a GTP_DUAL is placed in the Far-End PMA loopback mode, the TX side of the other channel no longer operates reliably. Do not attempt nor expect reliable use of the second channel while the first is in 100 loopback. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 199: Far-End Pcs Loopback

    PCI Express compliant loopback mode that echoes the received data back to the sender. Figure 9-5 illustrates this configuration. Far-End GTP Serial Parallel TX-PMA TX-PCS Serial Parallel RX-PMA RX-PCS UG196_c9_05_082906 Figure 9-5: Far-End PCS Loopback Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 200 Chapter 9: Loopback www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 201: Analog Design Guidelines

    MGTAVTTRX is the analog supply for the receiver circuits MGTAVTTRX and termination of the GTP_DUAL tile. MGTAVTTRXC is the analog supply for resistor MGTAVTTRXC calibration and standby circuit of the entire device. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 202: Description

    49.9 Ω resistor with 1% tolerance. Each LXT or SXT device requires a filter circuit on the MGTAVTTRXC pin, which powers the resistor calibration circuit of the device. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 203 The Virtex-5 Data Sheet provides the required exact voltage level and tolerance ranges of these analog supplies. Adequate filtering must be provided as illustrated in Figure 10-3. Xilinx recommends the use of separate (adjustable) voltage regulators for each supply circuit until full characterization results are available. Note: The voltage levels in...
  • Page 204 1. This analog supply MUST be sourced directly from a dedicated regulator. Derived voltages from other supplies or resistor voltage dividers are NOT permitted. Figure 10-4: Power Filter Network for MGTAVTTRXC www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 205 Virtex-5 Data Sheet. This value can be overwritten independently for each transceiver by using the TERMINATION_CTRL and TERMINATION_OVRD attributes. This feature is intended for experimental purposes only. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 206 37.6 48.8 61.0 36.6 47.6 59.5 35.7 46.5 58.1 34.9 45.4 56.8 34.1 44.4 55.5 33.3 43.4 54.2 32.5 42.5 53.1 31.8 41.5 51.9 31.2 40.7 50.9 30.5 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 207: Refclk Guidelines

    MGTREFCLKP – MGTREFCLKN. MGTREFCLKP – MGTREFCLKN IDIFF –V UG196_c10_07_110206 Figure 10-7: Differential Clock Input Voltage Swing, Peak-to-Peak Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 208 If the common mode voltage of the driving clock source is different from the common mode voltage of the differential reference clock input pair, then AC coupling capacitors are mandatory to prevent device degradation and/or other damage. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 209: Gtp Reference Clock Checklist

    The connection between the dedicated clock input pin pair of a GTP_DUAL primitive and the outputs of the oscillator or buffer MUST be a point-to-point connection. No bifurcated transmission lines, “T-stubs”, branches, or daisy-chaining are permitted! Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 210: Switching Between Two Different Reference Clocks

    Unused Reference Clock Inputs of GTP_DUAL Tiles for Clock Forwarding It is recommended to connect the unused differential input pin clock pair to ground or left floating (both MGTREFCLKP and MGTREFCLKN). 1. A wander is low-frequency jitter. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 211: Examples Of Vendors And Devices

    Ferrite beads, Provides component S parameters capacitors for simulation support, design libraries for Signal Integrity tools (http://www.component.tdk.com /tvcl_sparam.php) Texas http://www.ti.com Voltage Instruments regulators, PLLs, buffer Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 212: Providing Power

    PLL of the GTP_DUAL primitive, are especially sensitive to power supply noise. When designing a complete Power Distribution System (PDS), the PSRR of the whole system and of each regulator, is load-current and frequency dependent. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 213: Description

    Because the capacitor on the output of the regulator is part of the regulator control loop, this capacitor not only impacts the regulator stability but the PSSR as well. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 214: Regulator Design Guidelines

    1. If the current rating of a ferrite is maxed out, the magnetic material of the ferrite body is in saturation, which impacts its ability to suppress high frequencies. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 215: Capacitor Selection Guidelines

    MGTRXN/MGTRXP and MGTTXN/MGTTXP can be left floating. If the unused GTP_DUAL tiles are not used for clock forwarding, all analog supplies pins must be powered but do not require filtering. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 216: Selectio-To-Gtp Crosstalk Guidelines

    I/O bank to GTP transceiver pairing. Table 10-5: Aggressive I/O Banks GTP_DUAL FF665 FF1136 FF1738 MGT112 MGT114 MGT116 12,16 MGT118 12,18 MGT120 12/20 MGT122 MGT124 12,20 12/20 MGT126 MGT128 MGT130 MGT132 24/5 MGT134 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 217 MGT112 MGT114 T5, W4 MGT118 AB5, AD5 Table 10-7: SelectIO Adjacent to MGTCLK (FF665 Packages) GTP_DUAL 1 mm 1.4 mm 116_REFCLK 112_REFCLK J5, L5 114_REFCLK R5, U5 118_REFCLK Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 218 Table 10-9: SelectIO Adjacent to MGTCLK (FF1136 Packages) GTP_DUAL 1 mm 1.4 mm 124_REFCLK E7, E9 120_REFCLK 116_REFCLK G5, J5 112_REFCLK 114_REFCLK 118_REFCLK 122_REFCLK 126_REFCLK AK6, AK8 Notes: 1. GTP_DUAL only available on XC5LX110T devices. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 219 120_REFCLK 116_REFCLK L5, N5 112_REFCLK 114_REFCLK AC5, AE5 118_REFCLK AJ5, AL5 122_REFCLK 126_REFCLK 130_REFCLK AV8, AV10 134_REFCLK AV15 AV14, AV16 Notes: 1. GTP_DUAL only available on XC5LX330T devices. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 220 Chapter 10: GTP-to-Board Interface www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 221: Section 2: Board Level Design

    10 Gb/s design. This section includes the following chapters: “Design Constraints Overview” “PCB Materials and Traces” “Design of Transitions” “Guidelines and Examples” Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 222 Section 2: Board Level Design www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 223: Chapter 11: Design Constraints Overview

    At gigahertz signaling speeds, losses due to the transmission medium become significant due to greater signal attenuation with increasing frequency. The attenuation of the high- frequency components slow down the edge and reduce voltage swing, resulting in eye Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 224: Powering Transceivers

    1V. At these low voltages, it is important that noise levels on these supplies be kept at a minimum. For this reason, Xilinx recommends the use of point-of-load (POL) power distribution techniques. The POL approach places the power supplies right at the device being powered, hence the name.

  • Page 225: Regulator Selection

    FPGA. Apply the same techniques for 10 Gb/s trace design in Chapter 13, “Design of Transitions,” to these clock traces. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 226: Coupling

    SONET, which uses scrambling to ensure adequate symbol transitions but does not provide DC balance. The remainder of this section provides the theory needed to select a blocking capacitor value appropriate for the application. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 227 Pattern Dependant Jitter (PDJ) is the result of this skew. Figure 11-5 shows an overlay of V1 and V2 in the region of Figure 11-4 where the jitter is greatest and shows several key parameters. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 228 Pattern Dependent Jitter (PDJ) = 3.200 x 10-12 (0.01 UI) • Consecutive Identical Digits (N ) = 5 (guaranteed by 8B/10B) • ) = 75 Ω Termination Resistance (R TERM www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 229: Selectio To Serial Transceiver Crosstalk Guidelines

    When a design dictates that SelectIO signals with BGA adjacency to transceiver analog supply pins are to be used for high-drive/high-speed applications, the following guidelines apply: Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 230 Capacitive coupling in this area this area between active signal to power “via stub” (secondary) path and power via (primary) UG196_c11_07_013007 Figure 11-7: Via Structures for BGA Adjacent SelectIO Signals www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 231: Chapter 12: Pcb Materials And Traces

    FR4 traces can have a spread of impedance values with increasing frequency. While this spread can be less significant at 3.125 Gb/s, it can be a concern at 10 Gb/s operation. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 232: Loss Tangent

    This appears as a degradation in the rise and fall times. Skin Effect and Resistive Losses Xilinx, in partnership with Dr. Howard Johnson, has developed a two-part DVD tutorial on signal integrity techniques and loss budgeting for transceivers [Ref The skin effect is the tendency for current to flow preferentially near the outer surface of a conductor.

  • Page 233: Traces

    In this case, the differential traces must be designed to have an odd mode impedance (Z ) of 50Ω , resulting in a differential impedance (Z ) of 100Ω , because DIFF = 2 x Z DIFF Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 234 Z of 50Ω. The PCB manufacturer also provides the parameters necessary for the specific PCB layout. Some parameters can be calculated or www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 235: Trace Routing

    A plane split causes a suboptimal current return path and increases the current loop area, thereby increasing the inductance of the trace at the plane split, changing the impedance of the trace. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 236: Simulating Lossy Transmission Lines

    The connectors attached to cables should exhibit low parasitic inductance and capacitance for high bandwidth operation. Optimal Cable Length Xilinx provides cable characterization reports of CAT5/5E/6, Infiniband HSSDC2, and Serial ATA for designers to select the appropriate cable type based on performance at various lengths.

  • Page 237: Chapter 13: Design Of Transitions

    TDR port. If the signal propagation speed through the transmission line is known, the location of the excess capacitance or inductance along the channel can be calculated. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 238 Figure 13-3 shows the integration of the normalized TDR area. Shaded area goes into the integral for Equation 13-2 UG196_c13_03_051406 Figure 13-3: Integration of Normalized TDR Area www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 239: Bga Package

    Flip-chip package transitions are effectively invisible to 10 Gb/s signals. The longest package paths have some insertion loss, less than 1 dB worst-case. To allow full simulation of package effects, the Xilinx Signal Integrity Simulation kit provides extracted S-parameter models of the package.
  • Page 240 Using frequency domain analysis within HFSS, there is a 20 dB (10x) improvement in return loss using this technique. The approximately -40 dB/decade slope in Figure 13-8 shows good fit to the frequency response of a lumped capacitor. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 241 SMT pad without the ground plane cleared from underneath. The blue curve shows that clearing out the ground plane removes much of the excess capacitance. This improvement can be quantified using Equation 13-1 Equation 13-2. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 242 13-12, clearing the ground plane under SMT pads yields a significant improvement in the performance of an SMT pad transition. Excess capacitance is reduced by 15x and return loss is improved by 20 dB. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 243: Differential Vias

    Ground-Signal-Signal-Ground (GSSG) type differential via. Ground vias are connected to each ground plane in the stackup, while signal layers only contain pads for the entry and exit layers. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 244 For this and other configurations of differential vias, it is best to simulate a model using 3D field solver tools to ensure that performance targets are met. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 245: P/N Crossover Vias

    Some transceivers offer the ability to independently switch the polarity of the transmit and receive signal pairs. This functionality eliminates the need to cross over the P/N signals at Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 246: Sma Connectors

    Assembly guidelines are crucial in ensuring that the process of mating the connector to the board is well-controlled to give the specified performance. Xilinx uses Rosenberger SMA connectors almost exclusively because of their excellent performance and because of the points listed in the previous paragraph.
  • Page 247 -0.5 Time, ns UG196_c13_17_051406 Figure 13-17: Simulated TDR of 45 Degree Bends with Jog-Outs Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 248 Frequency, GHz UG196_c13_19_051406 Figure 13-19: Simulated Phase Response of 45 Degree Bends with Jog-Outs For wide traces, curved routing can also be helpful as shown in Figure 13-20. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 249 With Jog-outs No Jog-outs Turns & Jog-outs Turns 10 mV, 100 ps Per Div. Skew UG196_c13_20_051406 Figure 13-20: Measured TDR of 45 Degree Bends with and without Jog-Outs Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 250 Chapter 13: Design of Transitions www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 251: Chapter 14: Guidelines And Examples

    10 mils. With smaller antipads or longer via stubs, the excess capacitance is much greater. Because the Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 252: Bga Escape Example

    For backplane applications, in-line connectors such as the one shown in Figure 14-2, are the most common. Of these connectors, the most common mounting method is press-fit, although SMT connectors offer much better performance. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 253 Figure 14-3: Tyco Z-PACK HM-Zd Press-Fit Connector Internals Figure 14-4 shows an example design where the traces are preskewed to compensate for P/N length mismatches within the connector body. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 254 (ISI) effects from the greater impedance variation. These effects can be offset by the additional performance gained from larger antipads with less excess capacitance. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 255: Section 3: Appendices

    Section 3: Appendices “MGT to GTP Transceiver Design Migration” “OOB/Beacon Signaling” “8B/10B Valid Characters” “DRP Address Map of the GTP_DUAL Tile” “Low Latency Design” Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 256 Section 3: Appendices www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 257: Appendix A: Mgt To Gtp Transceiver Design Migration

    Table A-1: Transceivers per Device Virtex Device # of Transceivers Virtex-II Pro FPGA 4, 8, 12, 16, 20 Virtex-4 FPGA 8, 12, 16, 20, 24 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 258: Clocking

    Clock selection changed slightly across the first three generations of MGTs. In contrast, the GTP_DUAL tile significantly enhances clocking capabilities by adding dedicated clocks routing and MUXing resources. Figure A-1 shows how the reference clocks are selected for each device. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 259: Serial Rate Support

    UG196_a_01_011507 Figure A-1: Reference Clock Selection for Each Device Serial Rate Support As the Xilinx transceivers continue to migrate, so do the supported serial rates. Table A-3 shows the rates supported by each MGT and GTP transceiver. Table A-3: Serial Rate Support...
  • Page 260 8, 10, 16, 20, 32, 40 1, 2, 3, 4, 5 Divide by N Parameter TXOUTDIV2SEL, RXOUTDIV2SEL PLL_DIVSEL_REF Divide by N Values 1, 2, 4, 8, 16, 32 1, 2 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 261: Flexibility

    1. Nominal values. Refer to the device data sheets for values and operating conditions. 2. Depends on AC/DC coupling or termination options. See the device user guides for more details. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 262 7. RTERM and MGTVREF resistors should have 0402 or 0603 package size. Virtex-4 Power Supply Filtering UG196_a_03_011507 Figure A-3: Virtex-II, Virtex-II Pro, Virtex-4, Virtex-5 GTP Power Supply Filtering www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 263: Other Minor Differences

    Parallel Loopback (Tx → RX) Serial Pre-Driver – Serial Post-Driver – – Serial Digital Receiver – – External Data PMA-Only Parallel – – Loopback PCI Express Repeater – – Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 264: Serialization

    2. RXCLKCORCNT must go to 3'b101 before channel bonding is complete. Pre-emphasis, Differential Swing, and Equalization The differential signaling techniques are more robust in recent Xilinx transceivers. The Virtex-5 GTP transceiver adds ports to control TX characteristics to simplify reconfiguration.
  • Page 265 1. Signal optimization settings are independent between both GTP transceivers of a GTP_DUAL tile. GTP0 is indicated by the suffix “0” after the signal name, and GTP1 is indicated by the suffix “1” (for example RXENEQB0, RXENEQB1). Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com...
  • Page 266 Appendix A: MGT to GTP Transceiver Design Migration www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 267: Appendix B: Oob/Beacon Signaling

    COM sequence being received: COMWAKE sequences use 106.7 ns idles, and COMINIT/COMRESET sequences use 320 ns idles. A COM sequence is valid when it is received four times consecutively. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 268: Beacon Signaling In Pci Express

    GTP transceiver support for PCI Express beacons uses interface signals defined in the PHY Interface for the PCI Express (PIPE) Specification. Control logic in the FPGA manages the format of the beacon sequence. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 269 D17.0 000 10001 100011 1011 100011 0100 D18.0 000 10010 010011 1011 010011 0100 D19.0 000 10011 110010 1011 110010 0100 D20.0 000 10100 001011 1011 001011 0100 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 270: Appendix C: 8B/10B Valid Characters

    D17.1 001 10001 100011 1001 100011 1001 D18.1 001 10010 010011 1001 010011 1001 D19.1 001 10011 110010 1001 110010 1001 D20.1 001 10100 001011 1001 001011 1001 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 271 D17.2 010 10001 100011 0101 100011 0101 D18.2 010 10010 010011 0101 010011 0101 D19.2 010 10011 110010 0101 110010 0101 D20.2 010 10100 001011 0101 001011 0101 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 272: Appendix C: 8B/10B Valid Characters

    D17.3 011 10001 100011 1100 100011 0011 D18.3 011 10010 010011 1100 010011 0011 D19.3 011 10011 110010 1100 110010 0011 D20.3 011 10100 001011 1100 001011 0011 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 273 D17.4 100 10001 100011 1101 100011 0010 D18.4 100 10010 010011 1101 010011 0010 D19.4 100 10011 110010 1101 110010 0010 D20.4 100 10100 001011 1101 001011 0010 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 274: Appendix C: 8B/10B Valid Characters

    D17.5 101 10001 100011 1010 100011 1010 D18.5 101 10010 010011 1010 010011 1010 D19.5 101 10011 110010 1010 110010 1010 D20.5 101 10100 001011 1010 001011 1010 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 275 D17.6 110 10001 100011 0110 100011 0110 D18.6 110 10010 010011 0110 010011 0110 D19.6 110 10011 110010 0110 110010 0110 D20.6 110 10100 001011 0110 001011 0110 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 276: Appendix C: 8B/10B Valid Characters

    D17.7 111 10001 100011 0111 100011 0001 D18.7 111 10010 010011 0111 010011 0001 D19.7 111 10011 110010 1110 110010 0001 D20.7 111 10100 001011 0111 001011 0001 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 277 111 11011 110110 1000 001001 0111 K29.7 111 11101 101110 1000 010001 0111 K30.7 111 11110 011110 1000 100001 0111 Notes: 1. Used for testing and characterization only. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 278 Appendix C: 8B/10B Valid Characters www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 279 Attributes with TRUE/FALSE values use “1” to represent TRUE and “0” to represent FALSE. • Convert integer values to binary. Table D-1: Special Attribute Mappings Attribute UCF/HDL Attribute Value DRP Binary Value CHAN_BOND_MODE MASTER SLAVE CLK25_DIVIDER Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 280: Appendix D: Drp Address Map Of The Gtp_Dual Tile

    Appendix D: DRP Address Map of the GTP_DUAL Tile Table D-1: Special Attribute Mappings (Continued) Attribute UCF/HDL Attribute Value DRP Binary Value OOB_CLK_DIVIDER 10000 00000 PLL_DIVSEL_FB 00001 00010 00110 010000 PLL_DIVSEL_REF 000000 PLL_RXDIVSEL_OUT PLL_TXDIVSEL_COMM_OUT PLL_TXDIVSEL_OUT RX_LOS_INVALID_INCR www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 281: Drp Address By Attribute

    DRP Binary Value RX_LOS_THRESHOLD RX_SLIDE_MODE PCIE RX_STATUS_FMT SATA RXREC RX_XCLK_SEL RXUSR TXOUT TX_XCLK_SEL TXUSR DRP Address by Attribute Table D-2 lists the DRP addresses according to attribute name. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 282 Table D-2: DRP Address by Attribute Attribute AC_CAP_DIS_0 AC_CAP_DIS_1 ALIGN_COMMA_WORD_0 ALIGN_COMMA_WORD_1 CHAN_BOND_1_MAX_SKEW_0 CHAN_BOND_1_MAX_SKEW_1 CHAN_BOND_2_MAX_SKEW_0 CHAN_BOND_2_MAX_SKEW_1 CHAN_BOND_LEVEL_0 CHAN_BOND_LEVEL_1 CHAN_BOND_MODE_0 CHAN_BOND_MODE_1 CHAN_BOND_SEQ_1_1_0...
  • Page 283 Table D-2: DRP Address by Attribute (Continued) Attribute CHAN_BOND_SEQ_1_1_1 CHAN_BOND_SEQ_1_2_0 CHAN_BOND_SEQ_1_2_1 CHAN_BOND_SEQ_1_3_0 CHAN_BOND_SEQ_1_3_1 CHAN_BOND_SEQ_1_4_0 CHAN_BOND_SEQ_1_4_1 CHAN_BOND_SEQ_1_ENABLE_0 CHAN_BOND_SEQ_1_ENABLE_1 CHAN_BOND_SEQ_2_1_0 CHAN_BOND_SEQ_2_1_1 CHAN_BOND_SEQ_2_2_0...
  • Page 284 Table D-2: DRP Address by Attribute (Continued) Attribute CHAN_BOND_SEQ_2_2_1 CHAN_BOND_SEQ_2_3_0 CHAN_BOND_SEQ_2_3_1 CHAN_BOND_SEQ_2_4_0 CHAN_BOND_SEQ_2_4_1 CHAN_BOND_SEQ_2_ENABLE_0 CHAN_BOND_SEQ_2_ENABLE_1 CHAN_BOND_SEQ_2_USE_0 CHAN_BOND_SEQ_2_USE_1 CHAN_BOND_SEQ_LEN_0 CHAN_BOND_SEQ_LEN_1 CLK_COR_ADJ_LEN_0 CLK_COR_ADJ_LEN_1...
  • Page 285 Table D-2: DRP Address by Attribute (Continued) Attribute CLK_COR_DET_LEN_0 CLK_COR_DET_LEN_1 CLK_COR_INSERT_IDLE_FLAG_0 CLK_COR_INSERT_IDLE_FLAG_1 CLK_COR_KEEP_IDLE_0 CLK_COR_KEEP_IDLE_1 CLK_COR_MAX_LAT_0 CLK_COR_MAX_LAT_1 CLK_COR_MIN_LAT_0 CLK_COR_MIN_LAT_1 CLK_COR_PRECEDENCE_0 CLK_COR_PRECEDENCE_1 CLK_COR_REPEAT_WAIT_0...
  • Page 286 Table D-2: DRP Address by Attribute (Continued) Attribute CLK_COR_REPEAT_WAIT_1 CLK_COR_SEQ_1_1_0 CLK_COR_SEQ_1_1_1 CLK_COR_SEQ_1_2_0 CLK_COR_SEQ_1_2_1 CLK_COR_SEQ_1_3_0 CLK_COR_SEQ_1_3_1 CLK_COR_SEQ_1_4_0 CLK_COR_SEQ_1_4_1 CLK_COR_SEQ_1_ENABLE_0 CLK_COR_SEQ_1_ENABLE_1 CLK_COR_SEQ_2_1_0...
  • Page 287 Table D-2: DRP Address by Attribute (Continued) Attribute CLK_COR_SEQ_2_1_1 CLK_COR_SEQ_2_2_0 CLK_COR_SEQ_2_2_1 CLK_COR_SEQ_2_3_0 CLK_COR_SEQ_2_3_1 CLK_COR_SEQ_2_4_0 CLK_COR_SEQ_2_4_1 CLK_COR_SEQ_2_ENABLE_0 CLK_COR_SEQ_2_ENABLE_1 CLK_COR_SEQ_2_USE_0 CLK_COR_SEQ_2_USE_1 CLK_CORRECT_USE_0...
  • Page 288 Table D-2: DRP Address by Attribute (Continued) Attribute CLK_CORRECT_USE_1 CLK25_DIVIDER CLKINDC_B CLKNORTH_SEL CLKSOUTH_SEL COM_BURST_VAL_0 COM_BURST_VAL_1 COMMA_10B_ENABLE_0 COMMA_10B_ENABLE_1 COMMA_DOUBLE_0 COMMA_DOUBLE_1 DEC_MCOMMA_DETECT_0 DEC_MCOMMA_DETECT_1...
  • Page 289 Table D-2: DRP Address by Attribute (Continued) Attribute DEC_PCOMMA_DETECT_0 DEC_PCOMMA_DETECT_1 DEC_VALID_COMMA_ONLY_0 DEC_VALID_COMMA_ONLY_1 MCOMMA_10B_VALUE_0 MCOMMA_10B_VALUE_1 MCOMMA_DETECT_0 OOB_CLK_DIVIDER OOBDETECT_THRESHOLD_0 OOBDETECT_THRESHOLD_1 OVERSAMPLE_MODE PCI_EXPRESS_MODE_0 PCI_EXPRESS_MODE_1...
  • Page 290 Table D-2: DRP Address by Attribute (Continued) Attribute PCOMMA_10B_VALUE_0 PCOMMA_10B_VALUE_1 PCS_COM_CFG PCOMMA_DETECT_1 PLL_DIVSEL_FB PLL_DIVSEL_REF PLL_RXDIVSEL_OUT_0 PLL_RXDIVSEL_OUT_1 PLL_SATA_0 PLL_SATA_1 PLL_TXDIVSEL_COMM_OUT PLL_TXDIVSEL_OUT_0 PLL_TXDIVSEL_OUT_1...
  • Page 291 Table D-2: DRP Address by Attribute (Continued) Attribute PMA_CDR_SCAN_0 PMA_CDR_SCAN_1 PMA_RX_CFG_0 PMA_RX_CFG_1 PRBS_ERR_THRESHOLD_0 PRBS_ERR_THRESHOLD_1 RCV_TERM_GND_0 RCV_TERM_GND_1 RCV_TERM_MID_0 RCV_TERM_MID_1 RCV_TERM_VTTRX_0 RCV_TERM_VTTRX_1 REFCLK_SEL[2:0]...
  • Page 292 Table D-2: DRP Address by Attribute (Continued) Attribute RX_BUFFER_USE_0 RX_BUFFER_USE_1 RX_DECODE_SEQ_MATCH_0 RX_DECODE_SEQ_MATCH_1 RX_LOS_INVALID_INCR_0 RX_LOS_INVALID_INCR_1 RX_LOS_THRESHOLD_0 RX_LOS_THRESHOLD_1 RX_LOSS_OF_SYNC_FSM_0 RX_LOSS_OF_SYNC_FSM_1 RX_SLIDE_MODE_0 RX_SLIDE_MODE_1 RX_STATUS_FMT_0...
  • Page 293 Table D-2: DRP Address by Attribute (Continued) Attribute RX_STATUS_FMT_1 RX_XCLK_SEL_0 RX_XCLK_SEL_1 SATA_BURST_VAL_0 SATA_BURST_VAL_1 SATA_IDLE_VAL_0 SATA_IDLE_VAL_1 SATA_MAX_BURST_0 SATA_MAX_BURST_1 SATA_MAX_INIT_0 SATA_MAX_INIT_1 SATA_MAX_WAKE_0 SATA_MAX_WAKE_1...
  • Page 294 Table D-2: DRP Address by Attribute (Continued) Attribute SATA_MIN_BURST_0 SATA_MIN_BURST_1 SATA_MIN_INIT_0 SATA_MIN_INIT_1 SATA_MIN_WAKE_0 SATA_MIN_WAKE_1 TERMINATION_CTRL TERMINATION_OVRD TRANS_TIME_FROM_P2_0 TRANS_TIME_FROM_P2_1 TRANS_TIME_NON_P2_0 TRANS_TIME_NON_P2_1...
  • Page 295 Table D-2: DRP Address by Attribute (Continued) Attribute TRANS_TIME_TO_P2_0 TRANS_TIME_TO_P2_1 TX_BUFFER_USE_0 TX_BUFFER_USE_1 TX_DIFF_BOOST_0 TX_DIFF_BOOST_1 TX_SYNC_FILTERB TX_XCLK_SEL_0 TX_XCLK_SEL_1...

  • Page 296: Drp Address By Bit Location

    DRP Addresses 30 through 37 • Table D-10, DRP Addresses 38 through 3F • Table D-11, DRP Addresses 40 through 47 • Table D-12, DRP Addresses 48 through 4F www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 297 Do Not Modify Do Not Modify Do Not Modify Do Not Modify BOND_ REF[5] VTTRX_1 CFG_1[15] SEQ_2_4_1[2] CHAN_ RCV_TERM_ PMA_RX_ Do Not Modify Do Not Modify Do Not Modify Do Not Modify Do Not Modify BOND_ GND_1 CFG_1[14] SEQ_2_4_1[3] Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 298 SCAN_1[13] BURST_1[5] WAKE_1[1] SEQ_2_3_1[8] _1[29] _1[13] INCR_1[2] PLL_ PRBS_ERR_ PRBS_ERR_ RX_LOS_ Do Not PMA_CDR_ SATA_MAX_ SATA_MAX_ RXDIVSEL_ THRESHOLD THRESHOLD INVALID_ Modify SCAN_1[12] BURST_1[4] WAKE_1[0] OUT_1[1] _1[28] _1[12] INCR_1[1] www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 299 FROM_P2_1[4] Modify SEQ_1_1_1[9] P2_1[4] P2_1[4] ENABLE_1[4] 1[2] TRANS_ TRANS_ CHAN_BOND CLK_COR_ SATA_MIN_ TRANS_TIME_ Do Not CLK_COR_ TIME_NON_ TIME_TO_ _SEQ_2_ MAX_LAT_ WAKE_1[2] FROM_P2_1[3] Modify SEQ_1_1_1[8] P2_1[3] P2_1[3] ENABLE_1[3] 1[1] Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 300 BOND_SEQ_ SEQ_1_2_1[3] SEQ_1_4_1[7] SEQ_2_1_1[5] SEQ_2_3_1[9] SEQ_2_4_1[3] ENABLE_1[6] 1[4] 2_2_1[8] COMMA_ MCOMMA_ CHAN_ CLK_COR_ CLK_COR_ CLK_COR_ CLK_COR_ CLK_COR_ 10B_ENABLE 10B_VALUE_ BOND_SEQ_ SEQ_1_2_1[2] SEQ_1_4_1[6] SEQ_2_1_1[4] SEQ_2_3_1[8] SEQ_2_4_1[2] _1[5] 1[3] 2_2_1[9] www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 301 CFG[15] 1_3_1[4] 1_1_1[0] 1[3] _1[1] CHAN_ CHAN_ CHAN_ CHAN_ PCS_COM_ BOND_SEQ_ BOND_2_ TX_SYNC_ Do Not OOB_CLK_ BOND_SEQ_ BOND_SEQ_ 1_ENABLE_ MAX_SKEW FILTERB Modify DIVIDER[1] CFG[14] 1_3_1[5] 1_1_1[1] 1[4] _1[2] Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 302 CFG[3] MODE_0[1] 1_2_0[5] 1_4_0[9] 2_1_0[7] CHAN_ CHAN_ CHAN_ CHAN_ PCS_COM_ Do Not Do Not Do Not Modify BOND_ BOND_SEQ_ BOND_SEQ_ BOND_SEQ_ Modify Modify CFG[2] MODE_0[0] 1_2_0[4] 1_4_0[8] 2_1_0[6] www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 303 _VAL_0[0] SEQ_2_4_0[7] SEQ_2_2_0[3] SEQ_2_1_0[9] SEQ_1_3_0[1] SEQ_1_2_0[7] _2_0[5] 0[8] CLK_COR_ CHAN_ MCOMMA_ COM_BURST CLK_COR_ CLK_COR_ SEQ_1_ CLK_COR_ CLK_COR_ BOND_SEQ_2 10B_VALUE_ _VAL_0[1] SEQ_2_4_0[8] SEQ_2_2_0[4] ENABLE_ SEQ_1_3_0[2] SEQ_1_2_0[8] _2_0[4] 0[9] 0[1] Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 304 _0[0] 0[3] _0[5] P2_0[5] _P2_0[5] CLK_COR_ CLK_COR_ OOBDETECT_ TRANS_ TRANS_ TRANS_ Do Not SATA_MIN_ REPEAT_WAIT MAX_LAT_ THRESHOLD TIME_TO_P2 TIME_NON_ TIME_FROM Modify WAKE_0[5] _0[1] 0[4] _0[0] _0[6] P2_0[6] _P2_0[6] www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 305 0[5] _0[1] P2_0[1] _P2_0[1] 0[1] CHAN_ CLK_COR_ TRANS_ TRANS_ TRANS_ BOND_SEQ_ Do Not SATA_MIN_ SATA_MIN_ MAX_LAT_ TIME_TO_P2 TIME_NON_ TIME_FROM 2_ENABLE_ Modify WAKE_0[1] BURST_0[5] 0[0] _0[2] P2_0[2] _P2_0[2] 0[2] Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 306 BURST_0[2] SCAN_0[10] SCAN_0[26] _0[10] _0[26] 0[9] _4_0[5] RX_LOS_ PRBS_ERR_ PRBS_ERR_ PLL_ CHAN_ SATA_MAX_ PMA_CDR_ PCI_EXPRESS INVALID_ THRESHOLD THRESHOLD TXDIVSEL_ BOND_SEQ_2 BURST_0[3] SCAN_0[11] _MODE_0 INCR_0[0] _0[11] _0[27] OUT_0[0] _4_0[4] www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 307 Modify Modify Modify Modify Modify Modify PMA_RX_ RCV_TERM_ Do Not Do Not Do Not Do Not Do Not Do Not CFG_0[13] MID_0 Modify Modify Modify Modify Modify Modify Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 308 Appendix D: DRP Address Map of the GTP_DUAL Tile www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 309: Appendix E: Low Latency Design

    GTP transceiver. The values in the Block Number column correspond to the circled numbers in Figure E-1. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...

  • Page 310: Gtp Receiver Latency

    GTP transceiver. The values in the Block Number column correspond to the circled numbers in Figure E-2. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...
  • Page 311 1. 1 cycle = 1 clock cycle at the RXUSRCLK rate. 2. When the RX buffer is bypassed, 10-bit internal data width is necessary, therefore, INTDATAWIDTH = 1. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 312 Appendix E: Low Latency Design www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 313: Appendix F: Advanced Clocking

    Chapter 10, “GTP-to-Board Interface,” REFCLK Guidelines for IBUFDS details. Note: Refer to Chapter 3, “Simulation” for the correct simulation-only attribute settings, SIM_PLL_PERDIV2 and SIM_GTPRESET_SPEEDUP, for simulating multirate designs. Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 314 REFCLK_SEL[2] 0x04 CLKSOUTH_SEL 0x04 CLKNORTH_SEL 0x04 To ensure that other attributes in DRP address 0x04 are not accidentally changed, use a read/modify/write procedure to change the MUX selectors. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

  • Page 315: Example

    Clock 4 clock. forward. Clock 2 0: Forward clock 2 1: Drive clock 3 northbound to tile A. southbound to tile C. Clock 3 Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007...
  • Page 316 Don’t Care: Clock 2 can Clock 1 1: Drive clock 1 not be sent more than northbound to tile E. three tiles from where it Clock 2 originates. www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide UG196 (v1.3) May 25, 2007...

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