Xilinx Virtex-6 FPGA User Manual page 306

Appendix B: DRP Address Map of the GTX Transceiver
Table B-1: Attributes DRP Address Map (Cont'd)
DADDR DRP Bits R/W
15:12
11:10 R/W
13h
9:0
15
14
13
R/W
14h
12
11
10
9:0
15:0 R/W
15h
15:11
R/W
16h
10:0
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306
Attribute Name
RX_SLIDE_AUTO_WAIT
CLK_COR_DET_LEN
CLK_COR_SEQ_2_3
DEC_VALID_COMMA_ONLY
ALIGN_COMMA_WORD
RX_DECODE_SEQ_MATCH
Reserved
DEC_MCOMMA_DETECT
DEC_PCOMMA_DETECT
CLK_COR_SEQ_2_4
PMA_CDR_SCAN
CDR_PH_ADJ_TIME
PMA_CDR_SCAN
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Attribute Bits Attribute Encoding
3:0 0-15
1
2
1:0
Reserved
4
9:0 0-1023
FALSE
TRUE
1
2
FALSE
TRUE
FALSE
TRUE
FALSE
TRUE
9:0 0-1023
15:0
4:0 0-31
26:16
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
DRP Binary
Encoding
(1)
1
00
01
11
(1)
1
0
1
0
1
0
1
0
1
0
1
(1)
1
(1)
1