Xilinx Virtex-6 FPGA User Manual page 111

X-Ref Target - Figure 2-6
Note:
floating, and the input port CEB is set to logic 0.
The User Constraints File (UCF) can be used to constrain the location of the transceivers
and the corresponding reference clock source location. For example, if Q(n) in
belongs to QUAD_114 of an LX75T-FF484 device (as shown in
constraints can be applied:
Figure 2-6
MGTREFCLK0[P/N] or MGTREFCLK1[P/N]. Users can set TXPLLREFSELDY[2:0] and
RXPLLREFSELDY[2:0] to the corresponding value as shown in
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
IBUFDS_GTXE1
MGTREFCLK0P I
MGTREFCLK0N
IB
IBUFDS_GTXE1
MGTREFCLK1P I
MGTREFCLK1N
IB
Figure 2-6: Multiple GTX Transceivers with Multiple Reference Clocks
The IBUFDS_GTXE1 diagram in
## Set placement for the corresponding GTXE1 instances
INST rocketio_wrapper_i/gtx0_rocketio_wrapper_i/gtxe1_i
INST rocketio_wrapper_i/gtx1_rocketio_wrapper_i/gtxe1_i
INST rocketio_wrapper_i/gtx2_rocketio_wrapper_i/gtxe1_i
INST rocketio_wrapper_i/gtx3_rocketio_wrapper_i/gtxe1_i
## Reference clock constraints. Assign the IBUFDS_GTXE1 input nets to the
## package pins for the corresponding dedicated clock sources
## MGTREFCLK0[P/N]_114 or MGTREFCLK1[P/N]_114.
NET MGTREFCLK0N LOC=U3;
NET MGTREFCLK0P LOC=U4;
NET MGTREFCLK1N LOC=R3;
NET MGTREFCLK1N LOC=R4;
shows that the TX PLL and RX PLL of each transceiver can be sourced by either
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O
O
Figure 2-6 is a simplification. The output port ODIV2 is left
Reference Clock Selection
Q
(n)
GTXE1
MGTREFCLKTX[0]
MGTREFCLKRX[0]
MGTREFCLKTX[1]
MGTREFCLKRX[1]
GTXE1
MGTREFCLKTX[0]
MGTREFCLKRX[0]
MGTREFCLKTX[1]
MGTREFCLKRX[1]
GTXE1
MGTREFCLKTX[0]
MGTREFCLKRX[0]
MGTREFCLKTX[1]
MGTREFCLKRX[1]
GTXE1
MGTREFCLKTX[0]
MGTREFCLKRX[0]
MGTREFCLKTX[1]
MGTREFCLKRX[1]
UG366_c2_08_081109
Figure 2-6
Figure 1-6, page 43), these
LOC=GTXE1_X0Y0;
LOC=GTXE1_X0Y1;
LOC=GTXE1_X0Y2;
LOC=GTXE1_X0Y3;
Figure 2-3, page 105.
111