Xilinx Virtex-6 FPGA User Manual page 31
Gtx transceivers
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- Manual (381 pages) ,
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- Getting started manual (77 pages)
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Table 1-1: Port and Attribute Summary (Cont'd)
RX Clock Divider Control
RX Margin Analysis
RX Polarity Control
RX Oversampling
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Port/Attribute
Attributes:
•
CDR_PH_ADJ_TIME
•
PMA_CDR_SCAN
•
PMA_RX_CFG
•
RX_EN_IDLE_HOLD_CDR
•
RX_EN_IDLE_RESET_FR
•
RX_EN_IDLE_RESET_PH
•
RX_EYE_SCANMODE
•
RXPLL_DIVSEL_OUT
Ports:
•
MGTREFCLKFAB[1]
•
O
•
ODIV2
•
PHYSTATUS
•
RXRATE[1:0]
•
RXRATEDONE
•
RXRECCLK
•
RXRECCLKPCS
Attributes:
•
RX_EN_RATE_RESET_BUF
•
RXPLL_DIVSEL_OUT
•
RXRECCLK_CTRL
•
TRANS_TIME_RATE
Ports:
•
RXDATA[31:0]
Attributes:
•
RX_EYE_OFFSET
•
RX_EYE_SCANMODE
Ports:
•
RXPOLARITY
Ports:
•
RXENSAMPLEALIGN
•
RXOVERSAMPLEERR
Attributes:
•
PMA_RX_CFG
•
RX_OVERSAMPLE_MODE
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Port and Attribute Summary
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