Xilinx Virtex-6 FPGA User Manual page 105

Figure 2-3
single GTXE1 primitive. The TXPLLREFSELDY and RXPLLREFSELDY ports are required
when multiple reference clocks are used. A single reference clock is most commonly used.
In this case, the TXPLLREFSELDY and RXPLLREFSELDY ports can be connected to 000,
and the Xilinx software tools handle the complexity of the multiplexers and associated
routing. See
X-Ref Target - Figure 2-3
The four GTX transceivers that make up a Quad share two dedicated reference clock pin
pairs. The user design accesses these reference clocks by instantiating IBUFDS_GTXE1
primitives. These reference clocks can be used locally by any of the four GTX transceivers
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
shows the detailed view of the reference clock multiplexer structure within a
Single External Reference Clock Use Model
GTX Transceiver
TXPLLREFSELDY[2:0]
MGTREFCLKTX[0]
MGTREFCLKTX[1]
NORTHREFCLKTX[0]
NORTHREFCLKTX[1]
SOUTHREFCLKTX[0]
SOUTHREFCLKTX[1]
GREFCLKTX 0
PERFCLKTX 1
RXPLLREFSELDY[2:0]
MGTREFCLKRX[0]
MGTREFCLKRX[1]
NORTHREFCLKRX[0]
NORTHREFCLKRX[1]
SOUTHREFCLKRX[0]
SOUTHREFCLKRX[1]
GREFCLKRX 0
1
PERFCLKRX
Notes:
1. The CORECLK multiplexer is controlled by software. If GREFCLK is connected, software configures
the multiplexer to use GREFCLK. If the PERFCLK is connected, software configures the multiplexer
to use PERFCLK. There is no user-controllable attribute to switch the multiplexer. Only one of the
inputs can be connected at a time.
2. The CAS_CLK input to the RX PLL is not used or configured.
Figure 2-3: GTX Transceiver Detailed Diagram
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0
1
2
3
Out
4
5
6
CORECLK
Out
7
See
Note 1
0
1
2
3
Out
4
5
6
CORECLK
Out
7
See
Note 1
Default Configuration
Reference Clock Selection
for more information.
TX PLL TX PLL REFCLK
CAS_CLK
RX PLL RX PLL REFCLK
(2)
NC
UG366_c2_02_051509
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