Xilinx Virtex-6 FPGA User Manual page 176

Chapter 3: Transmitter
Table 3-31: TX Configurable Driver Ports (Cont'd)
Port
TXPREEMPHASIS[3:0]
TXP
TXN
TXSWING
Notes:
1. As per PHY Interface for the PCI Express Architecture, PCI Express 2.0, Revision 0.5, August 2008.
Table 3-32
Table 3-32: TX Configurable Driver Attributes
Attribute
TX_DEEMPH_0[4:0]
TX_DEEMPH_1[4:0]
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176
Dir Clock Domain
In Async Transmitter Pre-Cursor TX Pre-Emphasis Control
user specified. All listed values (dB) are typical.
Out TX Serial Clock TXP and TXN are differential complements of one another
(Pad) forming a differential transmit output pair. These ports represent
the pads. The locations of these ports must be constrained (see
Implementation, page
design.
In Async TX swing control for PCI Express PIPE Interface
mapped internally to TXDIFFCTRL/TXBUFDIFFCTRL.
defines the TX configurable driver attributes.
Type
5-bit This attribute has the value of TXPOSTEMPHASIS[4:0] that has to be
Binary mapped when TXDEEMPH = 0. TX_DEEMPH_0[4:0] =
TXPOSTEMPHASIS[4:0]. The default is 11010 (nominal value).
Do not modify this value.
5-bit This attribute has the value of TXPOSTEMPHASIS[4:0] that has to be
Binary mapped when TXDEEMPH = 1. TX_DEEMPH_1[4:0] =
TXPOSTEMPHASIS[4:0]. The default is 10000 (nominal value).
Do not modify this value.
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Description
[3:0] dB (Pre-Emphasis Magnitude)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
41) and brought to the top level of the
0: Full Swing
1: Low Swing
Description
Virtex-6 FPGA GTX Transceivers User Guide
.
The default is
0.15
0.3
0.45
0.61
0.74
0.91
1.07
1.25
1.36
1.55
1.74
1.94
2.11
2.32
2.54
2.77
(1)
. This signal is
UG366 (v2.5) January 17, 2011