Xilinx Virtex-6 FPGA User Manual page 152

Chapter 3: Transmitter
X-Ref Target - Figure 3-18
RESETDONE0
TXGEARBOXREADY0
TXHEADER
TXSTARTSEQ0
TXDATA0
TXUSRCLK20
Figure 3-18: TX Gearbox Internal Sequence Mode, 4-Byte Interface, 64B/67B
X-Ref Target - Figure 3-19
TXHEADER
TXSTARTSEQ0
TXUSRCLK20
TXGEARBOXREADY0
TXDATA0
Figure 3-19: TX Gearbox Internal Sequence Mode, 2-Byte Interface, 64B/66B
The sequence of transmitting data for the internal sequence counter mode is:
1.
2.
3.
4.
5.
6.
7.
8.
9.
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152
1
81300de0 18c72cde
GEARBOXREADY Low
Data still taken on this cycle.
1
1ca6 919a 4a95 2e71
GEARBOXREADY Low
Data still taken on this cycle.
GEARBOXREADY Low
Data not latched by Gearbox.
Hold TXSTARTSEQ Low.
Assert TXRESET and wait until the reset cycle is completed.
TXGEARBOXREADY goes High.
During reset, place the appropriate header data on TXHEADER and the initial data on
TXDATA. This state can be held indefinitely in readiness for data transmission.
Drive TXSTARTSEQ High and place the first valid header information on TXHEADER
and data on TXDATA.
Continue to drive header information and data until TXGEARBOXREADY goes Low.
When TXGEARBOXREADY goes Low, drive the last 2 (or 4) bytes of data and the
header information (4-byte input mode).
Hold the data pipeline for four bytes of data (one TXUSRCLK2 cycle for a 4-byte input
or two TXUSRCLK2 cycles for a 2-byte input).
On the next TXUSRCLK2 cycle, drive data on the TXDATA inputs.
TXGEARBOXREADY is asserted High on the previous TXUSRCLK2 cycle.
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19928750
GEARBOXREADY Low
Data not latched by Gearbox.
58c3 1298
GEARBOXREADY Low
Data not latched by Gearbox.
GEARBOXREADY High
Data latched by Gearbox.
Virtex-6 FPGA GTX Transceivers User Guide
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GEARBOXREADY High
Data latched by Gearbox.
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dac0 406e 036b
UG366_c3_9_051509
UG366 (v2.5) January 17, 2011