Xilinx Virtex-6 FPGA User Manual page 114

Chapter 2: Shared Transceiver Features
X-Ref Target - Figure 2-8
The PLL input clock selection is described in
outputs feed the TX and RX clock divider blocks, which control the generation of serial and
parallel clocks used by the PMA and PCS blocks. These blocks are described in
Clock Output Control, page 167
Figure 2-9
input clock is recommended for the best jitter performance. The input clock can be divided
by a factor of M before feeding into the phase frequency detector. The feedback dividers,
N1 and N2, determine the VCO multiplication ratio and the PLL output frequency. A lock
indicator block compares the frequencies of the reference clock and the VCO feedback
clock to determine if a frequency lock has been achieved.
X-Ref Target - Figure 2-9
Note:
Equation 2-1
Equation 2-2
resides in the clock divider block.
Table 2-7
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114
Figure 2-8: Top-Level PLL Architecture
illustrates a conceptual view of the PLL architecture. A low phase noise PLL
PLL
CLKIN
Phase
/ M
Frequency
Detector
In Figure 2-9, a value of 4 or 5 for the feedback divider (N1*N2) of the PLL is not supported.
shows how to determine the PLL output frequency (GHz).
f
PLLClkout
shows how to determine the line rate (Gb/s). D is the PLL output divider that
f
LineRate
lists the actual attribute and commonly used divider values.
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TX
TX
Clock
PLL
Dividers
RX
RX
Clock
PLL
Dividers
Reference Clock Selection, page
and RX Fabric Clock Output Control, page
Lock
Indicator
Charge
Loop
Pump Filter
/ N2 / N1
Figure 2-9: PLL Detail

N1 N2

--------------------- -
= f
PLLClkin
M

f 2
PLLClkout
= ---------------------------------- -
D
Virtex-6 FPGA GTX Transceivers User Guide
TX PMA
TX PCS
RX PMA
RX PCS
UG366_c2_05_051509
102. The PLL
TX Fabric
207.
PLL
LOCKED
PLL
CLKOUT
VCO
UG366_c2_06_051509
Equation 2-1
Equation 2-2
UG366 (v2.5) January 17, 2011