Xilinx Virtex-6 FPGA User Manual page 20

Chapter 1: Transceiver and Tool Overview
X-Ref Target - Figure 1-1
TX TX
TX OOB Pre/
Driver
and Post
PCIe emp
PISO
PLL
TX-PMA
PLL
RX
DFE
EQ
RX
CDR
RX OOB
SIPO
RX-PMA
Figure 1-1: Virtex-6 FPGA GTX Transceiver Simplified Block Diagram
Details about the different functional blocks of the transmitter and receiver including their
use models are described in
Figure 1-2
(XC6VLX75T).
Additional information on the functional blocks in
locations:
www.BDTIC.com/XILINX
20
Phase
Adjust
Polarity
FIFO &
Over-
sampling
PCIe
Beacon
SATA
OOB
To RX Parallel
Data (Near-End
(Far-End PMA Loopback)
PCS Loopback)
Pattern
Checker
Polarity
Over-
sampling
Chapter 3,
shows the GTX transceiver placement in an example Virtex-6 device
www.xilinx.com
TX
Gearbox
Pattern
Generator
From RX Parallel Data
From RX Parallel Data
(Far-End PCS Loopback)
Loss of Sync
RX PIPE Control
Comma
Detect
and
RX Status Control
Align
Gearbox
Elastic
Buffer
10B
/8B
Transmitter, and Chapter 4,
Figure 1-2
Virtex-6 FPGA GTX Transceivers User Guide
TX PIPE
Control
FPGA
TX
Interface
8B/
10B
TX-PCS
FPGA
RX
Interface
RX
RX-PCS
UG366_c1_01_051509
Receiver.
is available in the following
UG366 (v2.5) January 17, 2011